Cross point memory array using distinct voltages

Details Cross point memory array using distinct voltages Cross point memory array using distinct voltages

2002-12-26

2004-12-14

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S069000

Reexamination Certificate

active

06831854

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory, and more specifically to memory employing a cross point array.
2. Description of the Related Art
Conventional nonvolatile memory requires three terminal MOSFET-based devices. The layout of such devices are not ideal, usually requiring feature sizes of 8f
2
for each memory cell, where f is the minimum feature size.
However, not all memory elements require three terminals. Certain complex metal oxides (CMOs), for example, can retain a resistive state after being exposed to an electronic pulse, which can be generated from two terminals. U.S. Pat. No. 6,204,139, issued Mar. 20, 2001 to Liu et al., incorporated herein by reference for all purposes, describes some perovskite materials that exhibit such characteristics. The perovskite materials are also described by the same researchers in “Electric-pulse-induced reversible resistance change effect in magnetoresistive films,” Applied Physics Letters, Vol. 76, No. 19, 8 May 2000, and “A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films,” in materials for the 2001 Non-Volatile Memory Technology Symposium, all of which are hereby incorporated by reference for all purposes.
Similarly, the IBM Zurich Research Center has also published three technical papers that also discuss the use of metal oxide material for memory applications: “Reproducible switching effect in thin oxide films for memory applications,” Applied Physics Letters, Vol. 77, No. 1, 3 Jul. 2000, “Current-driven insulator-conductor transition and nonvolatile memory in chromium-doped SrTiO
3
single crystals,” Applied Physics Letters, Vol. 78, No. 23, 4 Jun. 2001, and “Electric current distribution across a metal-insulator-metal structure during bistable switching,” Journal of Applied Physics, Vol. 90, No. 6, 15 Sep. 2001, all of which are hereby incorporated by reference for all purposes.
Similarly, magnetic RAM (MRAM) requires only two terminals to deliver a magnetic field to the memory element. Other two terminal devices include Ovonic Unified Memory (OUM), which uses chalcogenic layers of material, and various types of ferroelectric memory. With only two terminals, it has been theorized that memory can be arranged in a cross point architecture.
However, mere recognition that a two terminal memory element is theoretically capable of being placed in a cross point array does not solve many of the non-trivial problems associated with actually creating such a device.
SUMMARY OF THE INVENTION
The present invention provides a cross point memory array. In one embodiment, the memory array includes a first layer of conductive array lines, a second layer of conductive array lines and a plurality of memory plugs.
The first layer of conductive array lines is arranged so that they do not come into direct contact with each other. Similarly, the second layer of conductive array lines is arranged so that they do not come into direct contact with either each other or any of the conductive array lines of the first layer. The plurality of memory plugs are located at the intersections of the first layer of conductive array lines and the second layer of conductive array lines. Each memory plug is in electrical contact with one of the conductive array lines from the first layer and one of the conductive array lines from the second layer such that each memory plug is associated with a unique pair of conductive array lines.
A single memory plug can be selected by selecting a unique pair of conductive array lines that is associated with the single memory plug, the unique pair consisting of a first layer conductive array line and a second layer conductive array line and applying select voltages to the selected conductive array lines. A first select voltage is applied to the first layer conductive array line and a second select voltage is applied to the second layer conductive array line. An unselect voltage can be applied to the unselected conductive array lines in the first and second layers, the unselect voltage being approximately equal to the average of the first select voltage and the second select voltage.


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