Cross point memory array including shared devices for...

Details Cross point memory array including shared devices for... Cross point memory array including shared devices for...

2001-01-29

2002-03-12

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S171000

Reexamination Certificate

active

06356477

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to information storage devices. More specifically, the present invention relates to a data storage device including a resistive cross point memory cell array.
Consider the example of a Magnetic Random Access Memory (“MRAM”) device including a resistive cross point array of spin dependent tunneling (SDT) junctions, word lines extending along rows of the SDT junctions, and bit lines extending along columns of the SDT junctions. Each SDT junction is located at a cross point of a word line and a bit line. The magnetization of each SDT junction assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of ‘0’ and ‘1.’ The magnetization orientation, in turn, affects the resistance of the SDT junction. Resistance of the SDT junction is a first value (R) if the magnetization orientation is parallel and a second value (R+&Dgr;R) if the magnetization orientation is anti-parallel. The magnetization orientation of the SDT junction and, therefore, its logic value may be read by sensing its resistance state.
Sensing the resistance state of a single SDT junction in a resistive cross point array can be unreliable. All SDT junctions in the array are coupled together through many parallel paths. The resistance seen at one cross point equals the resistance of the SDT junction at that cross point in parallel with resistances of SDT junctions in the other rows and columns.
Moreover, if the SDT junction being sensed has a different resistance state due to the stored magnetization, a small differential voltage may develop. This small differential voltage can give rise to parasitic or “sneak path” currents. The parasitic currents can interfere with the sensing of the resistance states.
Parasitic currents are illustrated in
FIG. 1. A
selected SDT junction is represented by a first resistor
12
a
, and unselected SDT junctions are represented by second, third and fourth resistors
12
b
,
12
c
and
12
d
. The selected SDT junction lies at the cross point of selected word and bit lines
14
and
16
. The second resistor
12
b
represents the unselected SDT junctions along the selected bit line
16
, the third resistor
12
c
represents the unselected SDT junctions along the selected word line
14
, and the fourth resistor
12
d
represents the remaining SDT junctions. If, for example, all of the SDT junctions
12
have a nominal resistance of about R and if the array
10
has n rows and m columns, then the second resistor
12
b
will have a resistance of about R/(n−1), the third resistor
12
c
will have a resistance of about R/(m−1), and the fourth resistor
12
d
will have a resistance of about R/[(n−1)(m−1)].
During a read operation, the first resistor
12
a
may be selected by applying an operating potential Vs to the selected bit line
16
and a ground potential to the selected word line
14
. Consequently, a sense current Is flows through the first resistor
12
a
. However, the second, third and fourth resistors
12
b
,
12
c
and
12
d
are also coupled between the operating potential Vs and the ground potential; therefore, sneak path currents S
1
, S
2
and S
3
can flow through the second, third and fourth resistors
12
b
,
12
c
and
12
d
. Moreover, the resistances of the second, third and fourth resistors
12
b
,
12
c
and
12
d
are much smaller than the resistance of the selected (first) resistor
12
a
; therefore, the sneak path currents S
1
, S
2
and S
3
are larger than the sense current I
s
. Such sneak path currents S
1
, S
2
and S
3
can obscure the sense current I
s
during a read operation on the selected SDT junction.
There is a need to reliably sense the resistance states of memory elements in MRAM devices. More generally, there is a need to reliably sense the resistance states of memory elements in resistive cross point memory cell arrays.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a random access memory device includes a resistive cross point array of memory elements, and a sneak path blocking device coupled to the memory elements. The blocking device is shared by a group of the memory elements. Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.


REFERENCES:
patent: 5640343 (1997-06-01), Gallagher et al.
patent: 6097625 (2000-08-01), Scheuerlein
patent: 6130835 (2000-10-01), Scheuerlein
patent: 6191972 (2001-02-01), Miura et al.
patent: 6215707 (2001-04-01), Moyer
patent: 6256224 (2001-07-01), Perner et al.
patent: 6256247 (2001-07-01), Perner

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