Cross point interconnect structure with reduced area

Details Cross point interconnect structure with reduced area Cross point interconnect structure with reduced area

1995-04-26

1996-06-25

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, 364491, H03K 19177

Patent

active

055303781

ABSTRACT:
An erasable programmable logic device (EPLD) includes function blocks connected by a universal interconnect matrix (UIM). The UIM includes both a cross-point circuit and a multiplexer-based (MUX-based) circuit. The cross-point circuit includes intersecting first and second conductors programmably connected by memory cells having control gates connected to the first conductors, drains connected to the second conductors, and sources connected to ground. The MUX-based circuit includes third and fourth conductors programmably connected by pass-gates having first terminals connected to the third conductors, second terminals connected to the fourth conductors, and gates connected to memory cells. The UIM further includes multiple-input multiplexers having first input lines connected to the cross-point circuit, second input lines connected to the MUX-based circuit, and output lines connected to the input lines of the function blocks. The multiple-input multiplexers are programmable to selectively apply signals from either the cross-point circuit or the MUX-based circuit to the function block input lines.

REFERENCES:
patent: 4912342 (1990-03-01), Wong et al.
patent: 5028821 (1991-07-01), Kaplinsky
patent: 5039885 (1991-08-01), Goetting et al.
patent: 5241224 (1993-08-01), Pedersen et al.
patent: 5451887 (1995-09-01), El Ayat et al.
patent: 5457410 (1995-10-01), Ting
patent: 5469003 (1995-11-01), Kean

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