Cross-coupled transistor pair

Details Cross-coupled transistor pair Cross-coupled transistor pair

2001-12-06

2003-08-26

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S202000, C257S394000, C257S206000

Reexamination Certificate

active

06611009

ABSTRACT:

This application claims priority from Korean Patent Application No. 2000-80426, filed Dec. 22, 2000, the contents of which are hereby incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to cross-coupled transistor pairs and methods of constructing cross-coupled transistor pairs.
2. Description of Related Art
In conventional cross-coupled transistor pair layouts, significant differences may exist between the length of a line connecting a gate of a first transistor to a node of the second transistor and the length of a line connecting a gate of the second transistor to a node of the first transistor. As a result, a gate loading and a junction loading of the two transistors forming the cross-coupled transistor pair may differ from each other. When differences occur between the gate loading and the junction loading of the transistors, the cross-coupled transistor pair may not operate as desired.
FIG. 1
is a circuit diagram illustrating a conventional cross-coupled transistor pair configuration. The cross-coupled transistor pair includes a first PMOS transistor PM
1
and a second PMOS transistor PM
2
. The first PMOS transistor PM
1
includes a source that receives a power supply voltage VCC, a drain connected to a node “a”, and a gate connected to a node “b”. The second PMOS transistor PM
2
includes a source that receives the power supply voltage VCC, a drain connected to the node “b”, and a gate connected to the node “a”.
Operation of the cross-coupled transistor pair of
FIG. 1
is as follows. If a voltage of the node “a” has a logic “high” level and a voltage of the node “b” has a logic “low” level, the first PMOS transistor PM
1
is turned on and the power supply voltage VCC is applied to the node “a”. The second transistor PM
2
is thereby turned off. Alternatively, if a voltage of the node “a” has a logic “low” level and a voltage of the node “b” has a logic “high” level, the second PMOS transistor PM
2
is turned on and the power supply voltage VCC is applied to the node “b”. The first PMOS transistor PM
1
is thereby turned off. The cross-coupled transistor pair of
FIG. 1
therefore acts as a latch to latch levels of the nodes “a” and “b”.
FIGS. 2A
to
2
D are plan views schematically illustrating a conventional method of constructing the cross-coupled transistor pair of FIG.
1
. Referring to
FIG. 2A
, separate first and second active areas PM
1
A, PM
2
A, corresponding to the first and second PMOS transistors PM
1
, PM
2
, respectively, are arranged on a substrate (not shown).
As shown in
FIG. 2B
, a first gate area PM
1
G is then arranged longitudinally on a portion of the first active area PM
1
A between a first source area PM
1
S and a first drain area PM
1
D. A second gate area PM
2
G is longitudinally arranged on a portion of the second active area PM
2
A between a second source area PM
2
S and a second drain area PM
2
D. A terminal of the first gate area PM
1
G extends perpendicularly to the right of the first active area PM
1
A to connect to the second drain area PM
2
D. A terminal of the second gate area PM
2
G extends perpendicularly to the left of the second active area PM
2
A to connect to first the drain area PM
1
D. The first and second gate areas PM
1
G, PM
2
G are indicated by cross-hatching.
Subsequently, as shown in
FIG. 2C
, first and second metal lines PM
1
M
1
, PM
2
M
1
are arranged longitudinally on the first and second source areas PM
1
S, PM
2
S, respectively, to receive the power supply voltage VCC. Third and fourth metal lines PM
1
M
2
, PM
2
M
2
are longitudinally arranged on the first and second drain areas PM
1
D, PM
2
D to connect to the second and first gate areas PM
2
G, PM
1
G, respectively. The first and second gate areas PM
1
G, PM
2
G correspond to the first and second PMOS transistors PM
1
, PM
2
, respectively. The first through fourth metal lines PM
1
M
1
, PM
2
M
1
, PM
1
M
2
, PM
2
M
2
are indicated by reverse cross-hatching.
Referring to
FIG. 2D
, contacts CON
1
connect the first and second metal lines PM
1
M
1
, PM
2
M
1
to the first and second source areas PM
1
S, PM
2
S. Contacts CON
1
also connect the third and fourth metal lines PM
1
M
2
, PM
2
M
2
to the first and second drain areas PM
1
D, PM
2
D, and connect the first and second gate areas PM
1
G, PM
2
G to the fourth and third metal lines PM
2
M
2
, PM
1
M
2
, respectively. Unfortunately, the distance from the node “a” to a position “c” on the second gate area PM
2
G is different than the distance from the node “b” to a position “d” on the first gate area PM
1
G. As a result, the cross-coupled transistor pair may not operate as designed.
FIG. 3
is a circuit diagram schematically illustrating another conventional cross-coupled transistor pair configuration. Referring to
FIG. 3
, a cross-coupled transistor pair according to this configuration includes first and second PMOS transistors PM
3
, PM
4
. The first PMOS transistor PM
3
has a source connected to a data input/output (I/O) line DIO, a gate connected to a node “f”, and a drain connected to a node “e”. The second PMOS transistor PM
4
includes a source connected to an inverted data I/O line DIOB, a gate connected to the node “e”, and a drain connected to the node “f”. This cross-coupled transistor pair arrangement provides a current sense amplifier for a data I/O line pair DIO, DIOB of a semiconductor memory device.
FIGS. 4A
to
4
E are plan views schematically illustrating a method of constructing the cross-coupled transistor pair of
FIG. 3
, according to the prior art. Referring first to
FIG. 4A
, first and second active areas PM
3
A, PM
4
A, corresponding to the first and second transistors PM
3
, PM
4
, respectively, are separately arranged on a substrate (not shown). Referring to
FIG. 4B
, a first gate area PM
3
G is longitudinally arranged on a portion of the first active area PM
3
A between a first source area PM
3
S and a first drain area PM
3
D. A second gate area PM
4
G is longitudinally arranged on a portion of the second active area PM
4
A between a second source area PM
4
S and a second drain area PM
4
D. A terminal of the first gate area PM
3
G extends perpendicularly to the left of the first active area PM
3
A to connect to the second drain area PM
4
D. A terminal of the second gate area PM
4
G extends perpendicularly to the right of the second active area PM
4
A to connect to the first drain area PM
3
D. The first and second gate areas PM
3
G, PM
4
G are indicated using cross-hatching.
As shown in
FIG. 4C
, a first signal line BP
1
is arranged outside the active areas in a transverse direction to provide a connection between the first drain area PM
3
D, corresponding to the first PMOS transistor PM
3
, and the second gate area PM
4
G, corresponding to the second PMOS transistor PM
4
. A second signal line BP
2
is also arranged transversely outside the active areas to provide a connection between the second drain area PM
4
D, corresponding to the second PMOS transistor PM
4
, and the first gate area PM
3
G, corresponding to the first PMOS transistor PM
3
.
Next, as shown in
FIG. 4D
, first and second metal lines PM
3
M
1
, PM
4
M
1
, corresponding to the data I/O line pair DIO, DIOB (see FIG.
3
), are arranged longitudinally on the first and second source areas PM
3
S, PM
4
S, respectively. Third and fourth metal lines PM
3
M
2
, PM
4
M
2
are arranged longitudinally on respective ones of the first and second drain areas PM
3
D, PM
4
D to connect them to the first and second signal lines BP
1
, BP
2
, respectively. Fifth and sixth metal lines M
1
, M
2
are arranged outside the first and second active areas PM
3
A, PM
4
A to connect the first and second signal lines BP
1
, BP
2
to the second and first gate areas PM
4
G, PM
3
G, respectively.
Finally, as shown in
FIG. 4E
, contacts CON
2
are arranged to connect the first and second metal lines PM
3
M
1
, PM
4
M
1
to the first and second source areas PM
3
S, PM
4
S, respectively. Contacts CON
2
further connect the third and fourth metal lines PM
3

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