Cross-coupled dual rail dynamic logic circuit

Details Cross-coupled dual rail dynamic logic circuit Cross-coupled dual rail dynamic logic circuit

2000-04-20

2001-12-11

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S098000, C326S095000, C326S093000

Reexamination Certificate

active

06329846

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to digital logic devices, and in particular to dynamic logic circuits used in digital devices.
BACKGROUND OF THE INVENTION
A modern computer system typically comprises a central processing unit (CPU) and supporting hardware necessary to store, retrieve and transfer information, such as communications buses and memory. It also includes hardware necessary to communicate with the outside world, such as input/output controllers or storage controllers, and devices attached thereto such as keyboards, monitors, tape drives, disk drives, communication lines coupled to a network, etc. The CPU is the heart of the system. It executes the instructions which comprise a computer program and directs the operation of the other system components.
From the standpoint of the computer's hardware, most systems operate in fundamentally the same manner. Processors are capable of performing a limited set of very simple operations, such as arithmetic, logical comparisons, and movement of data from one location to another. But each operation is performed very quickly. Programs which direct a computer to perform massive numbers of these simple operations give the illusion that the computer is doing something sophisticated. What is perceived by the user as a new or improved capability of a computer system is made possible by performing essentially the same set of very simple operations, but doing it much faster. Therefore continuing improvements to computer systems require that these systems be made ever faster.
The overall speed of a computer system (also called the throughput) may be crudely measured as the number of operations performed per unit of time. Conceptually, the simplest of all possible improvements to system speed is to increase the clock speeds of the various components, and particularly the clock speed of the processor(s). E.g., if everything runs twice as fast but otherwise works in exactly the same manner, the system will perform a given task in half the time. Early computer processors, which were constructed from many discrete components, were susceptible to significant speed improvements by shrinking component size, reducing component number, and eventually, packaging the entire processor as an integrated circuit on a single chip. The reduced size made it possible to increase clock speed of the processor, and accordingly increase system speed.
Despite the enormous improvement in speed obtained from integrated circuitry, the demand for ever faster computer systems has continued. Speed increases may be obtained from improvements at nearly every level of computer design, from the high level architecture of the system to the level of the individual circuits themselves.
One innovation that has been attempted in recent years is dual rail dynamic logic circuitry. A dynamic logic circuit operates by charging a precharge node (which serves as a gate to a driver) during one phase of a clock, and evaluating the logic value of the circuit during a second phase of the clock. During the evaluation phase, the node is either discharged to ground, or not discharged (allowed to retain its original positive charge), depending on the logic values of the inputs. Dual rail dynamic logic uses complementary sets of inputs for discharging separate precharge nodes, to produce two complementary outputs, which in turn serve as inputs to the next logic stage.
Dual rail dynamic logic provides improved speed over standard dynamic logic, which in turn provides improved speed over static logic. However, like most innovations, dual rail dynamic logic comes with a price. Obviously, additional transistors and wires are needed to implement a dual rail design of the same logic circuitry. Dynamic logic is, by its nature, potentially susceptible to noise, due to the reliance on a small charge in the precharge node to place the output driver in the correct state when the precharge node is not discharged in the evaluation phase. The proliferation of wires and precharge nodes makes dual rail designs significantly more susceptible to noise
It would be desirable to obtain the speed advantages of dual rail dynamic logic without the noise sensitivity of conventional dual rail dynamic logic designs.
SUMMARY OF THE INVENTION
Logic functions using dual rail dynamic logic circuits are implemented by cross-coupling a pair shunt transistors to the outputs.
In the preferred embodiment, the precharge nodes provide input to the gates of respective inverter drivers, each inverter driver formed using CMOS technology as a p-channel field-effect transistor (pFET) and an n-channel field-effect transistor (nFET). The circuit's logic functions discharge the precharge nodes to ground. Therefore, one of the precharge nodes discharges to ground, while the other retains its positive precharge. The inverter drivers drive the discharged precharge node high, while the precharge node which retains its original charge is driven low. The shunt transistors are nFETs which connect the outputs of the inverter drivers to ground. The gate of each shunt transistor is driven by the output of the opposite inverter driver.
In dual rail dynamic logic, it is always the case that one of the outputs is driven by a discharged precharge node, while the other is driven by a precharge node which retains its original charge. In the preferred embodiment, the output which is driven by a discharged precharge node is relatively immune from noise, since there is a path from the precharge node to ground through several open transistors. The output driven by the discharged precharge node will turn on the shunt transistor for the complementary output, bringing that output to the correct logic value even if noise is present. The shunts only conduct current where noise has affected one of the outputs, and therefore there is no appreciable increase in power consumption. Furthermore, in the absence of noise, the shunts have negligible effect on circuit switching speed.
The details of the present invention, both as to its structure and operation, can best be understood in reference to the accompanying drawings, in which like reference numerals refer to like parts, and in which:


REFERENCES:
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patent: 5550490 (1996-08-01), Durham et al.
patent: 6087854 (2000-07-01), Potter
patent: 6090153 (2000-07-01), Chen et al.
patent: 6133761 (2000-10-01), Matsubara
patent: 6161166 (2000-12-01), Doing et al.
Mark N. Horenstein, Microelectronic Circuits And Devices. 1996 by Printice-Hall, INc.

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