Cross-coupled complementary bit lines for a semiconductor memory

Details Cross-coupled complementary bit lines for a semiconductor memory Cross-coupled complementary bit lines for a semiconductor memory

1990-05-08

1990-12-25

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365 51, 365 63, 365 69, 365206, G11C 506, G11C 702, G11C 1140

Patent

active

049808605

ABSTRACT:
A criss-crossed complementary bit line and cross-coupled pull-up means is disclosed. One bit line (26) is crossed with respect to another bit line (28) of a complementary bit line pair to reduce the effect of noise interference induced therein. P-channel cross-coupled pull-up transistors (154, 156) are connected between the bit lines (26, 28) at an intersection (148) to assure that when one bit line is pulled low by the readout of a memory cell (158), the other bit line is pulled to the supply voltage.

REFERENCES:
patent: 3303481 (1967-02-01), Kessler
patent: 3942164 (1976-03-01), Dunn
patent: 4238838 (1980-12-01), Wright et al.
patent: 4476547 (1984-10-01), Miyasaka
patent: 4493057 (1985-01-01), McElroy
patent: 4570241 (1986-02-01), Arzubi
patent: 4602355 (1986-07-01), Watanabe
patent: 4694428 (1987-09-01), Matsumura et al.
patent: 4733374 (1988-03-01), Furuyuma et al.

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