Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-06-04
2010-10-05
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07810060
ABSTRACT:
Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.
REFERENCES:
patent: 6178539 (2001-01-01), Papadopoulou et al.
patent: 6202181 (2001-03-01), Ferguson et al.
patent: 6247853 (2001-06-01), Papadopoulou et al.
patent: 6317859 (2001-11-01), Papadopoulou et al.
patent: 6738954 (2004-05-01), Allen et al.
patent: 6948141 (2005-09-01), Sayta et al.
patent: 7143371 (2006-11-01), Allen et al.
patent: 7260790 (2007-08-01), Allen et al.
patent: 7404159 (2008-07-01), Allen et al.
patent: 2001/0003427 (2001-06-01), Ferguson et al.
patent: 2002/0156550 (2002-10-01), Langford
patent: 2005/0021234 (2005-01-01), Han
patent: 2005/0168731 (2005-08-01), Shibuya et al.
patent: 2005/0172549 (2005-08-01), Allen et al.
patent: 2005/0240839 (2005-10-01), Allen et al.
patent: 2006/0190224 (2006-08-01), Allen et al.
patent: 2007/0294648 (2007-12-01), Allen et al.
patent: 2008/0059929 (2008-03-01), Papadopoulou et al.
patent: 2008/0127004 (2008-05-01), Allen et al.
patent: 2009/0031266 (2009-01-01), Papadopoulou et al.
patent: 2009/0100386 (2009-04-01), Allen et al.
patent: 2009/0113360 (2009-04-01), Bickford et al.
Papadopoulou et al., “Critical Area Computation Via Voronoi Diagrams,” IEEE Trans. Computer Aided Design, vol. 18, pp. 463-474, 1999.
Papadopoulou et al., “Critical Area Computation for Missing Material Defects in VLSI Circuits,” IEEE Trans. Trans. Semiconduct. Manufact., vol. 20, pp. 583-597, 2001.
Papadopoulou et al., “Critical Area Computation- A New Approach,” Proc. International Symposium on Physical Design, pp. 89-94, 1998.
Heng et al., “VLSI Yield Enhancement Techniques Through Layout Modification”, IBM T.J. Watson Research Center, pp. 1-15, 2000.
Venkataraman et al., “Trade-Offs Between Yield and Reliability Enhancement”, Proc. Of 1996 IEEE National Symp. On Defect and Fault Tolerance in VLSI Systems, pp. 67-75, 1996.
Allen, Jr. Robert J.
Papadopoulou Evanthia
Tan Mervyn Yee-Min
Chiang Jack
Gibb I.P. Law Firm LLC
International Business Machines - Corporation
Parihar Suchin
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