Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2011-08-02
2011-08-02
Nguyen, Thinh T (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S428000, C257S513000, C257SE21552
Reexamination Certificate
active
07989308
ABSTRACT:
The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches (10). In order to prevent voltage rises at sharp edges on the bottom of the isolation trenches, said edges are rounded in a simple process, part of the insulating layer (2) being isotropically etched.
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Eckoldt Uwe
Lerner Ralf
Oetzel Thomas
Duane Morris LLP
Nguyen Thinh T
X-FAB Semiconductor Foundries AG
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