Creating standard VHDL test environments

Details Creating standard VHDL test environments Creating standard VHDL test environments

2002-07-16

2004-11-02

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06813751

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to testing of digital designs defining integrated circuits in a hardware description language and, more specifically, to creating standard test environments for digital designs.
2. Description of the Related Art
The proliferation of modern electronics into our everyday life is due in large part to the existence, functionality and relatively low cost of advanced integrated circuits. As technology moves ahead, the sophistication and, consequently, the complexity of design processes of integrated circuits continually increases.
An important aspect of designing a complex integrated circuit is the ability to thoroughly test the design of the integrated circuit to verify that the design complies with desired architectural, performance and design parameters. Verifying the logical correctness of a digital design and debugging the design, if necessary, are important steps in most digital design processes.
Integrated circuits are tested either by actually building networks or by simulating networks on a computer. Testing a complex integrated circuit requires the generation of a large number of instruction sequences to assure that the integrated circuit behaves properly under a wide variety of circumstances. Accordingly, testing has become a very costly and time-consuming segment of the overall design process as designs become increasingly complex. Since the fabrication of integrated circuits requires considerable-time and correction of mistakes is quite costly, it becomes necessary to test and simulate a design before the design is actually built.
Prior to testing, a designer creates a high-level description of an integrated circuit utilizing a hardware description language (HDL), such as VHDL or Verilog. VHDL is a higher-level language for describing the hardware design of complex integrated circuits. The overall circuit design is frequently divided into smaller parts, hereinafter referred to as design entities, which are individually designed, often by different designers.
FIG. 10
illustrates an exemplary design of an entity
1200
of an integrated circuit as described using a HDL according to the state of the art. Entity
1200
comprises a plurality of interfaces
1220
,
1230
,
1240
, and
1250
and an architecture
1260
. In VHDL, entity
1200
may further comprise one ore more configurations (not shown). Each Interface
1220
,
1230
,
1240
and
1250
comprises a plurality of input and output ports, each input port for receiving an input signal
1270
and each output port for providing an output signal
1280
. A port may correspond to a pin on a corresponding integrated circuit or an edge connector on a board, and so on. The architecture
1260
describes the function of entity
1200
. Accordingly, if the entity
1200
exemplarily represents a NAND-gate, architecture
1260
would describe how the output signal
1280
of the NAND-gate is created using appropriate input signals
1270
. In a minimum configuration, entity
1200
may only comprise one interface having one input port and one output port.
Different entities of a digital design, for example, a plurality of entities
1200
according to
FIG. 10
, may be combined in a hierarchical manner to create an overall model. The hierarchical design technique is very useful in managing the enormous complexity of an overall design. Another advantage of this approach is that errors in a design entity are easier to detect when that entity is tested in isolation.
A problem arises, however, when the overall model is tested as a whole. Compound errors may occur which mask other individual errors. Further, the enormity of modern digital design complexity makes the errors in each design entity difficult to recognize. Therefore, although the hierarchical nature of VHDL eases the development and modeling phases of complex designs, problems with obtaining accurate and comprehensive test results of the overall design remain unresolved.
A useful method of addressing design complexity is to test digital designs at several levels of abstraction. At the functional level, system operation is described in terms of a sequence of transactions between registers, adders, memories and other functional units. Testing at the functional level is utilized to verify the high-level design of high-level systems. At the logical level, a digital system is described in terms of logic elements such as logic gates and flip-flops. Testing at the logic level is utilized to verify the correctness of the logic design. At the circuit level, each logic gate is described in terms of its circuit components such as transistors, impedances, capacitances, and other such devices. Testing at the circuit level provides detailed information about voltage levels and switching speeds.
For testing the design description, a designer may create a testbench. Such a testbench defines a test circuit and is constructed using the HDL. The testbench normally comprises the entity to be tested, i.e., a corresponding entity description, bus-functional models for driving the interfaces of the entity described by the entity description and an observer for observing the testing results. The bus-functional models and the observer are themselves separate modules. The testbench is used to apply stimulus to the design description and to verify whether the design operates as expected. The testbench is only used to verify input and output of the entity and is, accordingly, interface, i.e., hardware specific. Thus, the testbench has no architectural knowledge of the entity.
In current design processes, the testbench is manually generated by the designer and may then be instantiated by testcases for testing the corresponding entity description. However, manually creating testbenches for a large number of entity descriptions of a complex digital design is very time consuming and cumbersome for the designer. Furthermore, when migrating from one abstraction level to another in a digital design process, e.g., from the logical level to the circuit level, a testbench created at the logical level for testing a specific entity description may not be useable for testing the specific entity description at the circuit level as, for instance, corresponding interfaces of the entity description have been modified. Consequently, testbenches must either be modified or new testbenches must be created.
Therefore, there is a need to improve the creation of testing environments for digital designs in order to test and simulate a digital design more efficiently and effectively before the design is actually build.
SUMMARY OF THE INVENTION
The present invention generally is directed to a method, system and article of manufacture for testing of digital designs defining integrated circuits in a HDL and, more specifically, for creating standard test environments for digital designs. A digital design may comprise one or more entity descriptions describing different entities or blocks of the integrated circuit in the HDL. Tags are added to each entity description and used to generate procedure calls and a testbench for testing the corresponding entity.
One embodiment provides a method of creating an entity description for use in an automated testing environment, the entity description defining an entity of an integrated circuit in a hardware description language, the entity of the integrated circuit comprising at least one interface having a plurality of ports each associated with a pre-determined function. The method comprises, for at least one port of the plurality of ports, associating at least one specific procedure call with the at least one port, the specific procedure call defining the pre-determined function of the at least one port.
Another embodiment provides a method of generating a procedure call from an entity description, the entity description defining an entity of an integrated circuit in a hardware description language, the entity of the integrated circuit comprising at least one interface having a plurality of ports each a

Affiliated with

Also associated with

Rating

Creating standard VHDL test environments does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Creating standard VHDL test environments, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Creating standard VHDL test environments will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3278405