CRC code generation circuit, code error detection circuit and CR

Details CRC code generation circuit, code error detection circuit and CR CRC code generation circuit, code error detection circuit and CR

1997-03-26

1999-08-10

Baker, Stephen M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714807, H03M 1300

Patent

active

059352698

ABSTRACT:
When encoding data received by a dividing circuit and to be included in a CRC code word, the data is divided by a generator polynomial and remainder data resulting from the division is output from a plurality of parallel data output terminals of the dividing circuit. The remainder data is added to a CRC intrinsic value and "0" information in the adder to produce a sum. The sum is a CRC code for a CRC code word to be transmitted. When detecting code errors, data from a CRC code word is received by the dividing circuit, where the data is divided by the generator polynomial, and remainder data resulting from the division is output from the respective parallel data output terminals. The remainder data is added to the CRC intrinsic value and CRC code in the adder to produce a sum, and the sum is processed by a logical sum circuit to produce a logical sum output as a CRC flag. The CRC code generation and code error detection circuit generates CRC codes to be included in CRC code words at high speed and detects errors in received CRC code words at high speed.

REFERENCES:
patent: 4309721 (1982-01-01), Christopher
patent: 5245606 (1993-09-01), DeSouza
patent: 5321704 (1994-06-01), Erickson et al.
patent: 5745503 (1998-04-01), Kuusinen
Blahut, "Theory and Practice of Error Control Codes", Addison-Wesley Pub. Co., 1984, pp. 137-147, May 1984.
Sobski et al., "Parallel Encoder, Decoder, Detector, Corrector for Cyclic Redundancy Checking", ISCAS '92, vol. 6, pp. 2945-2948, Dec. 1992.

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