Crack resistant passivation layer

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate

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438784, 438778, 438958, H01L 21469

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active

057473897

ABSTRACT:
A method for making a device and the device itself which utilizes a passivation layer displaying improved crack resistance is disclosed. This is accomplished through the incorporation of boron into a PSG passivation layer. The temperature of the passivation deposition may need to be kept to a temperature low enough so that the boron compound used for the boron source does not decompose prior to reacting with other reactants.

REFERENCES:
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patent: 4574467 (1986-03-01), Halfacre et al.
Becker et. al., "Process and Film . . . borophosphosilicate glass"; J. Vac. Sci. Technol. B 4(3); May/Jun. 1986; pp. 732-744.
Wolf; "Silicon Processing for the VLSI era"; vol. 1; 1986; pp. 187-191.
"MMT's Chemical Vapor Deposition Equiqment Guide"; Microelectric Manufacturing and Testing; May 1988; pp. 44-45.
"Doped SiO.sub.2 deposition from TMP in ApCVD"; Bartholomew et. al.; European Transactions on Telecommunications and Related Technologies, vol. 2, No. 4, Mar./Apr. 1990, pp. 167-172.
"Optimization of APCVD TEOS/O.sub.3 process for SiO.sub.2 and BPSG"; Bartholomew et al.; Third Annual Dielectrics and CVD Metallization Symposium, Feb. 11-12, 1991; pp. 110-145.
Wolf, "Silicon processing for the VLSI Era", vol. 1: Process Technology, Lattice Press, 1986, pp. 182-186.

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