CPU write-back cache coherency mechanism that transfers data fro

Details CPU write-back cache coherency mechanism that transfers data fro CPU write-back cache coherency mechanism that transfers data fro

1997-03-20

1999-09-07

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711135, G06F 1212

Patent

active

059502274

ABSTRACT:
A writeback cache coherency control module that can allow systems that do not support cache, or support only writethrough cache, to operate with a processor that has writeback cache. The control module also maintains coherency between main memory and cache in a writeback subsystem.

REFERENCES:
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.

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