CPU write-back cache coherency mechanism that transeers data fro

Details CPU write-back cache coherency mechanism that transeers data fro CPU write-back cache coherency mechanism that transeers data fro

1996-11-15

1999-04-06

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711135, G06F 1212

Patent

active

058931546

ABSTRACT:
A writeback cache coherency control module that can allow systems that do not support cache, or support only writethrough cache, to operate with a processor that has writeback cache. The control module also maintains coherency between main memory and cache in a writeback subsystem.

REFERENCES:
patent: 4167782 (1979-09-01), Joyce et al.
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5210847 (1993-05-01), Thome et al.
patent: 5524234 (1996-06-01), Martinez, Jr. et al.

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