1997-12-08
1999-04-27
Sheikh, Ayaz R.
395309, 395500, G06F 1300
Patent
active
058988467
ABSTRACT:
A CPU interconnect system permits swapping of different CPUs in a computer without requiring that the different CPUs each be adapted to conform to a standard input/output bus. Translation between CPU input/output lines and a system bus is accomplished by a programmable logic circuit. A memory containing a configuration program for the programmable logic circuit is associated with each CPU desired to be swapped. Thus, when a CPU is swapped or upon the occurrence of any other convenient event, the programmable logic circuit may be loaded with the program to configure the programmable logic circuit to perform the translation required by a current CPU.
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Sheikh Ayaz R.
Wiley David A.
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