CPU expandability bus

Details CPU expandability bus CPU expandability bus

1999-12-20

2003-04-29

Thai, Xuan (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus expansion or extension

C710S312000

Reexamination Certificate

active

06557065

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a high speed and high bandwidth expandability bus that is compatible with various integrated and non-integrated central processing unit products.
BACKGROUND OF THE INVENTION
The current, “standard” state-of-the-art personal computer (“PC”) architecture has evolved, and continues to evolve, in response to the marketplaces demand for faster processing speeds and the quickest possible application response times. This is especially true for graphics and video intensive applications, such as, high-resolution graphic video games and streaming video programs. In addition, future processor designs that are currently being developed (for example, processors having integrated graphics co-processors), will operate at speeds far above existing bus transmission speeds. As a result, the demand for ever faster systems continues to grow. As in the past, a major limiting factor on how fast PCs can process and display information depends on how quickly the necessary information can be provided to and received from the central processor unit (“CPU”). The two major components that determine this response time are the speed of the random access memory (“RAM”) and the speed at which the bus can transmit the information in RAM to and from the CPU.
FIG. 1
is a generic block diagram of a hypothetical general PC architecture. In
FIG. 1
, a CPU
10
is coupled to a controller chip known as a “Northbridge” chip
20
by a front-side bus (“FSB”)
12
and the CPU
10
is also coupled to a level 2 cache RAM
50
by a back-side bus (“BSB”)
14
. Integrated in the CPU
10
is a level 1 cache RAM (not shown) that can transfer data at clock speeds equivalent to the CPU
10
. The “Northbridge” chip
20
is a Very Large Scale Integration (“VLSI”) chip
20
that provides the main system logic chip portion of the PC motherboard chipset
16
. The “chipset”
16
couples and controls all of the different parts of the PC motherboard and usually comprises the Northbridge chip
20
and a Southbridge chip
30
. The Northbridge chip
20
couples the FSB
12
from the CPU
10
to an Accelerated Graphics Port (“AGP”) bus
62
via an AGP (not shown), Intel AGP Interface Specification Revision 2.0, published May 4, 1998; a main memory bus
42
; a Peripheral Component Interconnect (“PCI”) bus
82
, PCI Special Interest Group (SIG) PCI Specification, Revision 20, published May 8, 1996; and a Small Computer Systems Interface (“SCSI”) bus
72
, ANSI X3.131-1994, Small Computer System Interface—2 (SCSI-2), published 1994. The graphics processor
60
is also coupled to a video monitor
64
by cable
66
and the graphics processor
60
is designed to provide rapid updates of the information that is displayed on video monitor
64
. The AGP bus
62
is also coupled to an AGP graphics processor
60
. The graphics processor
60
can, also, coupled to a video frame buffer RAM (not shown) by a video bus (not shown) for increased display speed. Finally, the Southbridge chip
30
is coupled to the PCI bus
82
by a stub
83
for communicating with the Northbridge chip
20
and a PCI-to-PCI bridge
80
.
The “Southbridge” chip
30
, which is also a VLSI chip, provides connections to current and old peripheral and communication devices and cards (not shown) including, but not limited to, for example, printers, modems, keyboards, mouses, CD-ROM drives, hard disk drives, floppy disk drives and Industry Standard Architecture (“ISA”) cards. Additionally, the Southbridge chip
30
provides the interfaces for Universal Serial Bus (“USB”) connectors (not shown), USB Specification, Version 1.1, published Sep. 23, 1998 and IEEE 1394 (also referred to as “Firewire”) connectors (not shown), IEEE Standard 1394-1995, Standard for a High Performance Serial Bus, published 1995.
FIG. 2
is a generic block diagram of a hypothetical state-of-the-art PC architecture that is very similar to the architecture in FIG.
1
. In
FIG. 2
, the only differences from
FIG. 1
occur in the chipset and, specifically, on how the Northbridge chip
20
and the Southbridge chip
30
are coupled to each other and on how the chipset
16
is coupled to the PCI bus
82
. In
FIG. 2
, the Northbridge chip
20
is now directly coupled to the Southbridge chip
30
by a proprietary bus
84
and the Southbridge chip
30
is directly coupled to the PCI bus
82
for communication over the PCI-to-PCI bridge
80
.
Unfortunately, current bus speeds are not keeping pace with the advances in processor speed and, as a result, the buses are becoming a major limiting factor in overall computer system speed and performance.
Since future system and processor designs (for example, multi-processor systems and processors having integrated graphics co-processors) will operate at speeds far above existing bus transmission speeds, the demand for ever faster bus systems will continue to grow. Therefore, it can be appreciated that a substantial need exists for a new fast, high bandwidth bus that is protocol independent and can couple multiple agents.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a computer system with a high speed, high bandwidth expandability bus for integrated and non-integrated CPU products. The computer system includes a processor, a chipset coupled to the processor and an expandability bus, which is coupled at one end to the chipset and at the other end to a replaceable electronic component. The expandability bus can be changeably configured to enable or disable bus mastering at both ends, as required, to operate with whichever replaceable electronic component is installed.


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