CPU and graphics unit with shared cache

Details CPU and graphics unit with shared cache CPU and graphics unit with shared cache

2006-04-04

2006-04-04

Chauhan, Ulka J. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Cache

C345S543000, C345S537000, C711S122000, C711S130000

Reexamination Certificate

active

07023445

ABSTRACT:
A method and mechanism for managing graphics data. A graphics unit is coupled to share a cache and a memory with a processor. The graphics unit is configured to partition rendered images into a plurality of subset areas. During the rendering of an image, data corresponding to subset areas of an image which require a relatively high number of accesses is deemed cacheable for a subsequent rendering. During a subsequent image rendering, if the graphics unit is required to evict data from a local buffer, the evicted data is only stored in the shared cache if a prior rendering indicated that the corresponding data is cacheable.

REFERENCES:
patent: 5949423 (1999-09-01), Olsen
patent: 6226012 (2001-05-01), Priem et al.
patent: 6239808 (2001-05-01), Kirk et al.
patent: 6266064 (2001-07-01), Snyder
patent: 6681297 (2004-01-01), Chauvel et al.
patent: 6801207 (2004-10-01), Tischler et al.
patent: 6801208 (2004-10-01), Keshava et al.
patent: 6819321 (2004-11-01), Hsieh et al.
patent: 6825848 (2004-11-01), Fu et al.
patent: 6842180 (2005-01-01), Maiyuran et al.
patent: 6891543 (2005-05-01), Wyatt
Thomas Pabst, “High-Tech and Vertex Juggling—NVIDIA's New GeForce3 GPU,” Feb. 27, 2001, 16 pages.
Alekey Berillo, “S3TC and FXT1 Texture Compression,” Copyright by Digit-Life.com, 1997-2003, 21 pages.
“Geode™ GX1 Processor Series Low Power Integrated x86 Solution,” National Semiconductor Corporation, Jun. 2002, 246 pages.
Ned Greene, Michael Kass, Gavin Miller, “Hierarchical Z-Buffer Visibility,” Siggraph Conference Proceedings, Aug. 1993.

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