Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1996-12-17
2000-07-04
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
G06F 1100
Patent
active
060853387
ABSTRACT:
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
REFERENCES:
patent: 5537541 (1996-07-01), Wibecan
patent: 5691920 (1997-11-01), Levine et al.
patent: 5768500 (1998-06-01), Agrawal et al.
patent: 5774724 (1998-06-01), Heisch
patent: 5802273 (1998-09-01), Levine et al.
Performance Monitor, PowerPC 604 RISC Microprocessor User's Manual, Chapter 9, pp. 9-1 through 9-11, IBM 1994.
Levine Frank Eliot
Moore Roy Stuart
Roth Charles Philip
Welbon Edward Hugh
Beausoliel, Jr. Robert W.
Elisca Pierre Eddy
England Anthony V. S.
International Business Machines - Corporation
Kordzik Kelly K.
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