Coverage metric and coverage computation for verification...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

10916258

ABSTRACT:
A method of electronic circuit design includes performing property verification for partitions of a design of an electronic circuit, selecting an outcome for each partition from a plurality of outcome categories, and computing coverage information for each element of the design based on the outcome.

REFERENCES:
patent: 6523151 (2003-02-01), Hekmatpour
patent: 6704912 (2004-03-01), Narain et al.
patent: 6708143 (2004-03-01), Kurshan
patent: 2002/0002698 (2002-01-01), Hekmatpour
patent: 2003/0121011 (2003-06-01), Carter
patent: 2004/0006751 (2004-01-01), Kawabe et al.
patent: 2004/0117746 (2004-06-01), Narain et al.
patent: 2004/0199887 (2004-10-01), Jain et al.
patent: 2004/0225974 (2004-11-01), Johnson

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Coverage metric and coverage computation for verification... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Coverage metric and coverage computation for verification..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Coverage metric and coverage computation for verification... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3853142

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.