Counterflow pipeline processor architecture for semi-custom appl

Details Counterflow pipeline processor architecture for semi-custom appl Counterflow pipeline processor architecture for semi-custom appl

1995-05-09

1997-12-30

Treat, William M.

395376, 395580, 395385, 395800, G06F 930, G06F 938

Patent

active

057040540

ABSTRACT:
A pipeline processor provides an instruction flow in a first direction and a data flow in an opposing direction. The pipeline processor includes program circuitry for issuing instructions in the first pipeline direction, with at least some instructions including user-defined operation codes. A result register stores and issues data in the opposing pipeline direction. Plural pipeline stages connect the program circuitry and the result register. A pipeline stage comprises instruction latch circuitry connected to receive and issue instructions in the first pipeline direction, and result latch circuitry connected to receive and issue result data in the opposing pipeline direction. Certain pipeline stages include a conversion module for determining a correspondence between a user-defined operation code and the pipeline operation code and, upon determining such a correspondence, causing the logic circuitry within the pipeline stage to commence execution of the pipeline operation code. Processor siding circuitry is coupled to at least some of the pipeline stages and performs logical operations on the result data in accordance with a pipeline operation code. Multi-threading and branch prediction capabilities are provided.

REFERENCES:
patent: 5572690 (1996-11-01), Sproull et al.
patent: 5600848 (1997-02-01), Sproull et al.
Sproull et al., "The Counterflow Pipeline Processor Architecture," IEEE Design &Test of Computers, v. 11, iss. 3, Fall 1994, pp. 48-59.
Sproull, et al., IEEE Design & Test of Computers FAU, 1994, pp.48-59 Counterflow Pipeline Processor Architecture.

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