Electrical pulse counters – pulse dividers – or shift registers: c – Particular parallel gating or clock signal
Reexamination Certificate
2006-10-17
2006-10-17
Callahan, Timothy P. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Particular parallel gating or clock signal
C377S107000
Reexamination Certificate
active
07123679
ABSTRACT:
A counter having enhanced counting speed is provided. The counter includes first through N-th output signal generators. The first output signal generator responds to a clock signal and outputs a first output signal in which a low level and a high level are output once per cycle of the clock signal. The second output signal generator responds to the clock signal and the first output signal and outputs a second output signal in which a low level and a high level are output every two cycles of the clock signal. The third output signal generator responds to the clock signal and the second output signal and outputs a third output signal in which a low level and a high level are output every four cycles of the clock signal. The N-th output signal generator responds to the clock signal and the N−1th output signal and outputs an N-th output signal in which a low level and a high level are output every 2N−1(where N is a natural number greater than 1) cycles of the clock signal. The first through N-th output signals represent logic values of an N-bit counter in which the first output signal is the least significant bit and the N-th output signal is the most significant bit. A synchronous or non-synchronous counter according to the present invention has reduced delay time, thereby ensuring a spacious operation margin in the design of peripheral circuits of the counter.
REFERENCES:
patent: 4521898 (1985-06-01), Akram
patent: 4845727 (1989-07-01), Murray
patent: 5432830 (1995-07-01), Bonnot
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patent: 99-080027 (1999-05-01), None
Callahan Timothy P.
Cox Cassandra
Samsung Electronics Co,. Ltd.
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