Count/address generation circuitry

Details Count/address generation circuitry Count/address generation circuitry

1999-12-30

2003-07-29

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C711S219000, C711S221000, C365S236000

Reexamination Certificate

active

06601158

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of electronics. More specifically, the invention relates to the use of counters and address generators.
2. Background Information
The format of the instructions provided to a given processor model (e.g., central processing unit, digital signal processor, etc.) specify, among other things, the ways in which users indicate on what data the processor is to operate. One such way is for the instruction format to include one or more fields whose contents designate internal processor register(s) storing the desired data. Another such way is referred as addressing modes. Examples of addressing modes include immediate addressing, absolute addressing, direct addressing, indirect addressing, etc. In immediate addressing, the instruction format includes a field that contains the actual data to be operated on by the CPU. In absolute addressing, the instruction format includes an encoded field that identifies the address of the data. In direct addressing, the instruction format includes a field whose contents (an offset) are added to a predefined base address to acquire the address. In indirect addressing, the instruction format includes a field whose contents designate an internal processor register whose contents are to be used as the address. In at least one DSP, the instruction format for indirect addressing also provides for a field used to indicate that the address and/or the contents of the designated register should be modified by one (up or down), an offset, or an index. See Texas Instruments, Inc. book
TMS
320
C
54
X DSP Reference Set, Volume
1:
CPU and Peripherals,
Literature Number SPRU131F (April 1999).
All of the above addressing modes, except the immediate and absolute addressing modes, require the use of additional instruction cycles to generate the addresses. Although the immediate and absolute addressing modes do not require additional instruction cycles to generate an address, they do require the use of a significantly larger number of instruction bits than the other addressing modes. These additional bits limit the number of operands that can be specified by a given instruction and/or require very large instructions. The feeding of a processor very large instructions reduces the number of instructions that can be provided to the processor in any given period of time, as thus slows processor throughput. In addition, the indirect addressing of the TMS320C54X DSP is mainly used when there is a need to step through sequential locations in memory in fixed size steps. This is true because this mode does not provide the capability to generate arbitrary sequences of addresses (non-fixed sized steps). However, there are application which require this flexibility.
BRIEF SUMMARY OF THE INVENTION
According to one embodiment of the invention, an apparatus is described that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper bound circuit of the first counter is coupled to the count computation circuit and upper bound circuit of the second counter. The apparatus also includes a lookup table addressed by the current count value of the first counter, as well as a combining circuit coupled to the output of the lookup table and to receive the current count value of the second counter.


REFERENCES:
patent: 5155823 (1992-10-01), Tsue
TMS320C54x DSP Reference Set, vol. 1: CPU and Peripherals, Literature No.: SPRU131F, Apr. 1999 (consisting of: Contents xvii-xxiv; Chapter 5 Data Addressing 5-1 to 5-29).

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