Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-27
2004-05-11
Lam, Tuan T. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C257S203000, C326S041000
Reexamination Certificate
active
06735755
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit (IC) design methods, and more particularly to cost and time saving IC design methods using pre-defined reusable modules.
IC manufacture technologies have been progressing in astonishing rates. Critical dimensions of IC technologies are reduced by one generation in every 18 months. Currently 0.18 &mgr;m (micrometers) technology is ready for mass production, while 0.13 or 0.09 &mgr;m technologies are on the way. These advanced technologies require super-fine resolution lithography masks to define the physical layout of circuits. The price of masks increases dramatically when critical dimension decreases. A typical mask set costs about $50 thousands for 0.35 &mgr;m technology, $500 thousands for 0.25 &mgr;m technology, and it is expected to cost more than $2 millions for future technologies. As IC manufacture technologies and IC designs are getting more and more complex, many products need to tape out multiple mask sets before they are ready for mass production. The costs for lithography masks become a heavy burden for IC manufacturers.
One common method to reduce this burden is to share the mask cost with other products at early developing stages. Multiple products designed by different companies are bundled together to share one mask set. After wafer production, each company obtains a small number of prototype devices for testing purpose. In order to collect enough designs to share the cost, such bundled productions are executed once every now and then. The waiting periods range from a few weeks to a few months. In the fast paced IC industry, the delay caused by such waiting may cost more than the money saved. Besides, we still need to pay for a complete mask set after the prototype is proven to be ready for mass production. This method is therefore useful only for limited cases.
The concept of pre-defined gate array modules was developed more than one decade ago as a cost saving method. A gate array contains a large number of transistors arranged in a pre-defined array structure. It is known that any logic equation can be translated into a gate array with proper metal connections. Products with different logic functions can be placed on the same gate array structure with different metal connections. It is therefore possible to share all the front-end manufacture procedures and masks. Individual user only needs to design and pay for metal masks. The gate array modules can be manufactured ahead of time by finishing all the front-end processes. An individual user only need to wait for back-end processing, saving the time needed for front-end wafer processing steps. This concept looked promising, but very few products were actually made by pre-manufactured gate array modules. The reason is simple.
FIG. 1
shows the layout of a typical IC chip. This chip contains a core circuit (
101
) block that is usually a combination of logic circuit modules (
102
) and memory modules (
103
). It also contains peripheral modules (
104
) such as input/output (I/O) devices (
105
), and bounding pads (
107
). The edges of the product are surrounded by seal rings (
109
). The seal rings are metal walls use to block moisture penetration. Out of the seal ring we need to reserve scribe lanes (
108
) for wafer cutting. It is true that almost any kind of logic circuit can be implemented by a gate array. If IC products can have nothing but logic circuits, it would be true that most of the resources can be shared. However, a prior art product needs all the other supporting structures. It is difficult to pre-define a complete module, including gate array and I/O devices, that can fit the requirements of many products simultaneously. For example, if we pre-manufacture a gate array module that has 200 thousand gates and 32 I/O pads. A product that needs 190 thousand gates and 28 I/O pads will fit nicely. However, a product that has 201 thousand gates or a product that has 33 I/O pads will need a larger gate array module. A product that has 120 thousand gates and 16 I/O will fit but there is a lot of waste. It is unlikely for any product to fit a particular pre-defined module exactly; most of time we need to select an unnecessary large pre-defined gate array module with a lot of wasted resource. One solution for the problem is to provide multiple pre-defined modules. Each product can select the module with the best fit. Assume that a company provides 4 pre-defined gate array modules. Each module has a pre-defined gate array and supporting I/O. These 4 modules are pre-defined and pre-manufactured. The front-end manufacture procedures are finished, while the customers only need to add metal lines to finish their products. The number of gates and the number of I/O pads for those modules are chosen so that they can adapt for different products as listed in the following table. Module name Gate number I/O number
Module name
Gate number
I/O number
Module 1
256K
64
Module 2
512K
128
Module 3
1M
208
Module 4
2M
256
Now assume that there are 8 different customer products. These products provide different logic functions so that they require different number of gates and I/O pads. The designers use the pre-defined gate array module with the lowest cost to fit their designs, as shown in the following table:
Gate
I/O
Chosen
% gate
Product
number
number
module
used
% I/O used
A
180K
32
1
70%
50%
B
380K
72
2
74%
56%
C
508K
128
2
99%
100%
D
1.34M
156
4
67%
61%
E
1.68M
256
4
84%
100%
F
1.04M
128
4
52%
50%
G
512K
68
2
100%
53%
H
274K
212
3
14%
83%
Only product C in the above example fully utilizes the resources provided by the pre-defined module it chooses. There are a lot of wasted resources for all the other products because they are forced to choose from pre-defined modules. Although we can save cost and time by using pre-defined modules, we are forced to pay for wasted resources. One possible solution is to define more modules, but that means we need to use more mask sets, which defeats the original cost saving purpose. Most products actual chose to use a full mask set to achieve optimum use in silicon area for mass production. Prior art pre-defined gate array modules are therefore useless except for a few special cases. It is therefore strongly desirable to have a pre-defined module that can be shared by many products while achieving high utilization rate for all individual products.
SUMMARY OF THE INVENTION
The primary objective of this invention is, therefore, to provide cost saving methods for designing integrated circuits. Another primary objective is to shorten manufacture time of IC products. The other objective is to provide effective supporting technologies, including testing, packaging, and input/output (I/O) methods, for products of the present invention. It is also a major objective of the present invention to shorten time-to-market for IC products using advanced manufacture technologies. These and other objectives are accomplished by novel pre-defined IC modules that are shared by many products without sacrificing utilization rate for individual products.
While the novel features of the invention are set forth with particularly in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed descriptions taken in conjunction with the drawings.
REFERENCES:
patent: 5386623 (1995-02-01), Okamoto et al.
patent: 5430734 (1995-07-01), Gilson
patent: 5512765 (1996-04-01), Gaverick
patent: 5760478 (1998-06-01), Bozso et al.
patent: 6157213 (2000-12-01), Voogel
Englund Terry L.
Lam Tuan T.
Lin Bo-In
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