Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1997-09-17
2000-08-01
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
G11C 2900
Patent
active
06098192&
ABSTRACT:
A cost reduced finite field processor is disclosed for computing the logarithm LOG.sub..alpha. (.alpha..sup.j) of an element of a finite field GF(2.sup.n) using significantly less circuitry than that required by a lookup table typically employed in the prior art. The result of the logarithm (i.e., the exponent of .alpha..sup.j) is represented as a binary number computed serially one bit per clock cycle. In one embodiment, combinatorial logic is used to compute bit 0 of the exponent. On each clock cycle, the exponent is shifted once to the right and bit of the exponent is extracted until the entire exponent has been computed. Shifting the exponent of a field element to the right is carried out by taking the square root of the element. The present invention requires at most n+1 clock cycles to compute LOG.sub..alpha. (.alpha..sup.j), with one embodiment requiring n/2 clock cycles. The circuitry for computing the square root of a field element and for computing bit 0 of the logarithm of a field element is significantly less than that required to implement the logarithm operation using a lookup table.
REFERENCES:
patent: 4410989 (1983-10-01), Berlekamp
patent: 4494234 (1985-01-01), Patel
patent: 4567568 (1986-01-01), Inagawa et al.
patent: 4989171 (1991-01-01), Hollmann
patent: 4994995 (1991-02-01), Anderson et al.
patent: 5420873 (1995-05-01), Yamagishi et al.
patent: 5467297 (1995-11-01), Zook
patent: 5590138 (1996-12-01), Iwamura
patent: 5757826 (1998-05-01), Fredrickson
patent: 5771246 (1998-06-01), Weng
patent: 5778009 (1998-07-01), Fredrickson et al.
patent: 5787099 (1998-07-01), Lan et al.
patent: 5831878 (1998-11-01), Ishida
Whiting, Douglas L., Bit-Serial Reed-Solomon Decoders in VLSI, California Institute of Technology, Aug. 1984, pp. 36-58.
Glover, N. and Dudley, T., Practical Error Correction Design for Engineers, Revised Second Edition, Cirrus Logic--Colorado, 1991, pp. 87-134.
Chase Shelly A
Cirrus Logic Inc.
Nguyen Hoa T.
Sheerin Howard H.
Shifrin Dan
LandOfFree
Cost reduced finite field processor for error correction in comp does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cost reduced finite field processor for error correction in comp, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cost reduced finite field processor for error correction in comp will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-674596