Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1999-04-05
2004-10-12
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S623000, C438S688000, C438S763000, C438S958000
Reexamination Certificate
active
06803327
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of Semiconductor integrated circuit devices, and more particularly to a cost effective method for forming a passivation layer on the top surface of interconnecting metal lines such that damage and extrusion in the surface of the passivation layer and SOG delamination over the metal lines are eliminated.
(2) Description of Prior Art
Metal lines of the various layers of conducting lines in a semiconductor device are separated by insulating layers such as silicon oxide and oxygen-containing polymers that are deposited using Chemical Vapor Deposition (CVD) techniques. The insulating layers are deposited over patterned layers of interconnecting lines where electrical contact between successive layers of interconnecting lines is established with metal vias created for this purpose in the insulating layers. Electrical contact to the chip is typically established by means of bonding pads that form electrical interfaces with patterned levels of interconnecting metal lines. Signal lines and power/ground lines can be connected to the bonding pads. After the bonding pads have been created on the surfaces of the chip package, the bonding pads are passivated and electrically insulated by the deposition of a passivation layer over the surface of the bonding pads. Passivation layer can contain silicon oxide/silicon nitride (SiO
2
/Si
3
N
4
) deposited by CVD. The passivation layer is patterned and etched to create openings in the passivation layer for the bonding pads after which a second and relatively thick passivation layer is deposited that further insulates and protects the surface of the chips from moisture and other contaminants and from mechanical damage during the final assembling of the chips. The chips are diced and further assembled on a single or multiple chip carrier, electrical contacts are then further established to the chips via the chip bonding pads.
The trend in the semiconductor industry to create ever denser circuit packages has resulted in packaging many integrated circuit chips in one package and to provide electrical interconnects between the chips within the package. One frequently used method where multiple chips are mounted in one package is the creation of a multi chip module (MCM). This approach has led to the creation of a multilayer structure in the MCM where active chips form the module and the chips are interconnected with a pattern of conducting lines. The conducting lines typically contain doped polysilicon, refractory metal silicides and metal. Via holes are provided that interconnect different layers of conducting lines. Typical dimensions for the conducing lines are a width of 6 to 20 um and a height of 5 to 10 um, conducting lines tend to be narrow in width and thick in the vertical direction. Signal lines are created in such a way as to reduce electrical cross talk between adjacent lines which requires that the conducting lines intersect under a 90-degree angle. To achieve proper creation of the layers of conducting lines and to minimize electrical interference between lines of different layers while at the same time meeting requirements of inter-layer insulation and device reliability, the different layers of conducting line patterns must be created in planes that are essentially flat and have good planarity.
Various materials have found application in the creation of passivation layers. Passivation layer can contain silicon oxide/silicon nitride (SiO
2
/Si
3
N
4
) deposited by CVD, passivation layer can be a photosensitive polyimide or can comprise titanium nitride. Another material often used for passivation layer is phosphorous doped silicon dioxide that is typically deposited over a final layer of aluminum interconnect using a Low Temperature CVD process. In recent years, photosensitive polyimide has frequently been used for the creation of passivation layers. Conventional polyimides have a number of attractive characteristics for their application in a semiconductor device structure such as the ability to fill openings of high aspect ratio, a relatively low dielectric constant (about 3.2), a simple process required for the depositing of a layer of polyimide, the reduction of sharp features or steps in the underlying layer, high temperature tolerance of cured polyimide. Photosensitive polyimides have these same characteristics but can, in addition, be patterned like a photoresist mask and can, after patterning and etching, remain on the surface on which it has been deposited to serve as a passivation layer. Typically and to improve surface adhesion and tension reduction, a precursor layer is first deposited by, for example, conventional photoresist spin coating. The precursor is, after a low temperature pre-bake, exposed using, for example, a step and repeat projection aligner and Ultra Violet (UV) light as a light source. The portions of the precursor that have been exposed in this manner are cross linked thereby leaving unexposed regions (that are not cross linked) over the bonding pads. During subsequent development, the unexposed polyimide precursor layer (over the bonding pads) is dissolved thereby providing openings over the bonding pads. A final step of thermal curing leaves a permanent high quality passivation layer of polyimide over the substrate.
For 0.5 um. and sub-half micron technologies, the spacing of the top metal becomes small enough to cause the creation of microscopic openings (keyholes) within the surface of deposited layers of passivation layers of Plasma Enhanced Oxide (PEOXIDE) or Plasma Enhanced Silicon Nitride (PESi
3
Ni
4
). The subsequently deposited photo resist that defines a passivation pattern will flow into these keyholes resulting in decreased thickness of the photo resist layer in the areas of the keyholes. This may result in damage to the passivation film during etching of the photoresist. The removal of the photoresist is a wet and dry strip process; Act
690
and NMP are used during this process and will also accumulate in the keyhole. The final step of alloying the remaining passivation layer requires elevated temperatures. The (in the keyhole) accumulated photoresist combined with the remnants of Act
690
and NMP (in the keyhole) evaporate at these elevated temperatures causing a violent chemical reaction and the extrusion of the photoresist from the keyhole.
FIGS. 1 through 7
show Prior Art processes used for the deposition of passivation layers over metal layers with the creation of bond pad contact.
FIG. 1
shows a Prior Art pattern of the top layer
12
of metal for interconnecting lines and the top layer
14
of metal for the formation of a bond pad. The layers of metal are deposited on the surface of a substrate
10
.
Conventional semiconductor device processing calls for the deposition of passivation layer over the entire top surface of the wafer. The passivation layer forms an insulating, protective layer that shields and protects the surface that it covers from mechanical and chemical damage during subsequent device assembly and packaging. The passivation layer must therefore have good adhesion to the underlying metal and any level of interlevel dielectric over which it is deposited, it must provide uniform step coverage so as not to hinder subsequent steps of planarization, it must be deposited in a uniform thickness, it must protest against mechanical damage such as surface scratch while it must also protect against moisture penetration, it must not introduce stress related problems while easy patterning of the passivation layer is required. It is clear that, in order to meet the requirements that are placed on the passivation layer; the passivation layer must be thick. In many applications, the passivation layer is therefore created using two depositions of passivation material.
FIG. 2
shows the deposition of a first passivation layer
16
of Plasma Enhanced oxide. This layer
16
is a blank deposition over the pattern
12
of the top layer metal for the interconnections and over the top layer metal
Cheu Shih-Shiung
Shen Chih-Heng
Sheu Yea-Dean
Berezny Nema
Chaudhari Chandra
Taiwan Semiconductor Manufacturing Company
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