Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2005-09-27
2005-09-27
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C714S723000, C714S724000, C714S725000
Reexamination Certificate
active
06950771
ABSTRACT:
Method and apparatus are disclosed for analyzing defect data produced in testing a semiconductor chip from a logic design. In various embodiments, input for processing is a first inspection data set that identifies a first set of physical locations that are associated with defects detected during fabrication of the chip. Also input is a second test data set that includes one or more identifiers associated with failing circuitry in the chip. A second set of physical locations is determined from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the design, and placement information associated with the blocks. Each of the one or more identifiers is associated with at least one of the blocks. Correspondences are identified between physical locations in the first inspection data set and the second set of physical locations.
REFERENCES:
patent: 2003/0046621 (2003-03-01), Finkler et al.
Chan Huan Gim, Jul. 8-12, 2002, Motorola Malaysia, “Physical and Failure Analysis of Integrated Circuits”, pp. 105-109.
Fan Yuezhen
Ling Zhi-Min
Tang Stephen Wing-Ho
Xu Jason
Barlow John
Khuu Cindy D.
Maunu LeRoy D.
Xilinx , Inc.
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