Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-02-27
2004-02-03
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06687885
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a layout pattern data correction device and, in particular but not exclusively, to the layout pattern data correction device for correcting pattern distortions caused during pattern formation by the utilization of a photo lithography technology, etching technique, or the like.
2. Description of the Related Art
Recently, a design rule of a semiconductor device has reached an accuracy level of 0.15 &mgr;m, which is smaller than the wavelength of light emitted from a light source (0.248 &mgr;m in the case of a KrF excimer laser) that is largely used in association with a stepper. Under such conditions, the resolution tends to be extremely deteriorated and, accordingly, the use has been made of a special lithography technology such as a modified illumination technology to improve the resolution. Although effective to improve the resolution, the use of the special lithography technology is ineffective to achieve a high fidelity reproduction of a pattern. In addition, the size of the pattern changes due to a difference in condensation and rarefaction of the pattern, when the pattern is fine.
As one solution to the above problems, OPC (Optical Proximity Effect Correction) is widely used in which a design layout pattern is modified so as to obtain a desired pattern. The OPC is available in three types; a model based OPC, a rule based OPC, and the combination thereof. In the model based OPC technique, a design layout pattern is modified based on a simulation test result. In the rule based OPC technique, a design layout pattern is modified based on a predetermined design rule (OPC rule) with regards paid to graphic characteristics of the design layout pattern such as width of each patterns, distance between the adjacent patterns, and distance from the corner of one pattern to other patterns. The combined OPC technique is that the model based and rule based OPC techniques are combined together.
Since a complex OPC is required as the pattern becomes fine, an output pattern data which is obtained after the OPC has been made tends to contain complicated polygonal features. Accordingly, the output pattern data contain those of figures having protrusions, recesses and steps. When the number of such figures increases, the number of vertexes included in the figures increases, resulting in increase in amount of the data.
The conventional rule based OPC technique will now be described with reference to
FIGS. 5
,
6
,
21
,
22
,
23
, and
24
.
FIG. 5
shows the layout pattern data of metal lines. Recently, DRC (Design Rule Check) tool is used in the practice of the rule based OPC technique. Hereinafter, it is assumed that the OPC is aimed at increasing the width of the layout patterns at a location where the neighboring patterns are spaced a distance equal to or greater than a certain value (K1).
At first, the edges of the layout patterns spaced a smaller distance from each other than the certain value are extracted by using a spacing check function of the DRC tool. Referring, for example, to the layout patterns
18
and
19
shown in
FIG. 5
the edges
100
and
101
of the pattern
18
and the edge
102
of the pattern
20
, which are at a distance smaller than K1 from the edges of their adjacent patterns, are extracted by using the DRC tool as shown in FIG.
21
. Then, edges which have not been extracted because they are at a distance equal to or greater than K1 from adjacent patterns are extracted, and they are defined as the target edges to be corrected. As described above, Those target edges are shown in FIG.
6
.
Next, corrected patterns are to be formed. This can be accomplished by subjecting the target edges to sizing with the use of the DRC tool. The target edges are oversized by an amount desired to be corrected, as shown by
110
in
FIG. 23
, in the case where the OPC is aimed at increasing the width of the layout patterns. When the edge
28
(
FIG. 6
) is oversized, an acute angled recess
103
tends to be formed as shown in FIG.
22
. Then, a boolean operation is carried out between the resultant corrected patterns and the original patterns to which the OPC has not been subjected. In this case, the boolean operation is an OR (summing) operation between the resultant corrected patterns and the original patterns. After the boolean operation has been carried out, the corrected layout patterns in
FIG. 24
are obtained. As shown in
FIG. 24
, fine protrusions
105
, a recess
103
, and a step
106
are produced.
According to the above-described conventional rule based OPC, the resultant layout pattern includes the graphic patterns such as fine protrusions, recesses, and steps, with an increased number of vertexes in the graphic pattern. As a result, there has been a problem in that data amount of the resultant layout patterns becomes large.
SUMMARY OF THE INVENTION
In view of the foregoing numerous problems, the present invention has been devised to eliminate the foregoing problems and is to provide a layout pattern data correction device, a method of correcting the layout pattern data, and a computer readable medium in which a layout pattern data correction program is recorded, all which are effective to prevent fine protrusions, recesses, and steps from producing and to reduce the data amount.
According to one aspect of the invention, a layout pattern data correction device includes: (a) edge extracting means for extracting a first target edge to be corrected from an original layout pattern of a circuit; (b) edge modifying region setting means for setting an edge modifying region in which the first target edge is modified with a predetermined point in the first target edge taken as a center; (c) edge modifying means for modifying the first target edge within the edge modifying region into a second target edge to be corrected; (d) corrected pattern forming means for forming a corrected pattern based on the second target edge; and (e) boolean operation means for performing a predetermined boolean operation based on both of the original layout pattern and the corrected pattern.
The edge modifying means may include means for lengthening or shortening the first target edge so that one end of the first target edge aligns with a vertex within the edge modifying region.
The edge modifying region may include a plurality of vertexes; and the edge modifying means may include means for choosing a longest segment in segments which are formed by connecting any two vertexes of the plurality of vertexes within the edge modifying region, and modifying the first target edge into the longest segment as the second target edge.
The corrected pattern forming means may include means for measuring an angle between the second target edge and an edge not to be corrected which continues to the second target edge, and forming the corrected pattern in accordance with the angle.
The corrected pattern forming means may include means for modifying the second target edge and forming the corrected pattern which is surrounded with the modified second target edge and the original layout pattern, when the second target edge does not fit to an edge of the original layout pattern.
According to another aspect of the invention, a method of correcting layout pattern data includes the steps of: (a) extracting a first target edge to be corrected from an original layout pattern of a circuit; (b) setting an edge modifying region in which the first target edge is modified with a predetermined point in the first target edge taken as a center; (c) modifying the first target edge within the edge modifying region into a second target edge to be corrected; (d) forming a corrected pattern based on the second target edge; and (e) performing a predetermined boolean operation based on both of the original layout pattern and the corrected pattern.
The step of modifying the first target edge (c) may include the step of lengthening or shortening the first target edge so that one end of the first target edge aligns with a vertex within the ed
Bowers Brandon
Garbowski Leigh M.
McDermott & Will & Emery
Renesas Technology Corp.
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