Correcting a target address in parallel with determining...

Details Correcting a target address in parallel with determining... Correcting a target address in parallel with determining...

2011-01-25

2011-01-25

Rizk, Sam (Department: 2112)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S800000

Reexamination Certificate

active

07877647

ABSTRACT:
As disclosed herein, an interface for a device adapted to couple to an interconnect may comprise decode and error check logic and a plurality of decode logic units. The decode and error check logic may receive error check bits and a target address from the interconnect and may determine whether the target address was received in error. At least one of the decode logic units also may receive the error check bits and correct the target address using the error check bits in parallel with the decode and error check logic determining whether the target address was received in error.

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