Core voltage generator and method for generating core...

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

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Reexamination Certificate

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07417903

ABSTRACT:
Provided are a core voltage generator and a method for generating a core voltage in a semiconductor memory device. The core voltage generator includes a first discharge driver for discharging a core voltage terminal for an interval at which the voltage is higher than a target level, in response to a first enable signal activated for a first predetermined period after overdriving a bit line, and a second discharge driver for discharging the core voltage terminal for an interval at which the voltage at the core voltage terminal is higher than the target level by a predetermined threshold, in response to a second enable signal activated for a second predetermined period after overdriving the bit line, wherein the second predetermined period is shorter than the first predetermined period.

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Yannis P. Tsividis, Operation and Modeling of The MOS Transistor, 1987, McGraw-Hill, pp. 200-202.

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