Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-09-17
1999-12-14
Pan, Daniel H.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395566, 711147, G06F 1312, G06F 906
Patent
active
060028815
ABSTRACT:
A digital signal processing system comprising a central processing unit core 2, a memory 8 and a coprocessor 4 operates using coprocessor memory access instructions (e.g. LDC, STC). The addressing mode information within these coprocessor memory access instructions (P, U, W, Offset) not only controls the addressing mode used by the central processing unit core 2 but is also used by the coprocessor 4 to determine the number of data words in the transfer being specified such that the coprocessor 4 can terminate the transfer at the appropriate time. Knowledge in advance of the number of words in a transfer is also advantageous in some bus systems, such as those that can be used with synchronous DRAM. The Offset field within the instruction may be used to specify changes to be made in the value provided by the central processing unit core 2 upon execution of a particular instruction and also to specify the number of words in the transfer. This arrangement is well suited to working through a regular array of data such as in digital signal processing operations. If the Offset field is not being used, then the number of words to be transferred may default to 1.
REFERENCES:
patent: 4943915 (1990-07-01), Wilhelm et al.
patent: 5193159 (1993-03-01), Hashimoto et al.
XP-002061358, The Implementation of the ARM, Section 4.1.9 Coprocessor Data Transfer Instructions, S. B. Furber: "VLSI RISC Architecture and Organization", 1989, pp. 261-265.
Seal David James
Symes Dominic Hugo
York Richard
ARM Limited
Pan Daniel H.
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