Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
1999-09-30
2002-07-23
Valentine, Donald R. (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S183000, C205S205000
Reexamination Certificate
active
06423200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor device fabrication and, more particularly, to methods and apparatus for fabricating more reliable interconnect metallization lines.
2. Description of the Related Art
The semiconductor device fabrication process beings with the fabrication of semiconductor wafers. Each wafer is then placed through a multitude of processing steps in order to produce an array of semiconductor dies. As is well known, transistors are first fabricated over the semiconductor wafer and then multiple levels of metallization lines and conductive vias are formed to interconnect the transistors. When copper interconnect metallization lines are used, processes referred to as damascene and dual-damascene are used to form trenches and via holes in dielectric layers. As will be described below, there are several problems with the normal copper fill process.
Reference is now made to
FIG. 1A
, which illustrates a cross-section view of a patterned dielectric layer
100
. As shown, the dielectric layer
100
has a via hole
102
, and a trench
104
. A barrier layer
105
is typically deposited over the dielectric layer
100
and into the via hole
102
and the trench
104
. Typically, the barrier layer is a tantalum material, a tantalum nitride material, or a combination of both. A copper seed layer
106
is then blanket deposited over the barrier layer
105
so as to line the inner walls and surfaces within the via hole
102
and trench
104
. The copper seed layer is needed to promote good adhesion and establish a good electrical contact between copper interconnect lines. The copper seed layer
106
is typically deposited using either a chemical vapor deposition (CVD) technique or a physical vapor deposition (PVD) technique. Once the copper seed layer
106
is deposited, the wafer is moved out of the deposition chamber and introduced to atmospheric conditions and exposed to oxygen before beginning a bulk copper fill process. During this time, which can vary widely depending on process parameters and throughput factors, the copper seed layer
106
will naturally tend to oxidize due to the exposure to oxygen.
Although the oxidation of the copper seed layer does not affect the copper on the top surface of the dielectric layer
100
, the amount of copper deposited in the trench
104
and via hole
102
is substantially thinner and is therefore affected most by copper oxidation. For instance, if a layer having a thickness X is deposited for the seed layer
106
, only about 10% of X will actually be deposited on the walls
110
of the via hole
102
. It is believed that approximately 10 to 30 percent of the copper seed layer
106
is oxidized before the bulk copper fill operation is performed. As shown in
FIG. 1B
, a top region
106
a
of the copper seed layer
106
is oxidized, leaving only the lower portion
106
b
as non-oxidized copper. Once the copper seed layer
106
is formed, a bulk copper fill
108
is performed to fill in the remainder of the via hole
102
and trench
104
.
A problem with having the copper seed layer oxidize is that the oxidized top region
106
a
may introduce performance defects in the interconnect metallization lines. For instance, the quality of the electroplated bulk copper fill
108
may be compromised, and thus form a less than perfect material bond with the copper seed layer
106
. Not only may the bond suffer due to the excessive presence of copper oxide
106
a
, but there will be less true copper material on the walls
110
. Because the filled via is the interface to lower conductive metallization lines or transistor devices, such interfaces will most likely be compromised due to the reduction of copper seed material that is needed to promote good bonding to the electroplated copper fill
108
.
One solution to remove the oxidation is to move the wafer into an etch chamber to etch away the copper oxide build-up. Although this technique can remove the copper oxide, etching also removes some of the copper seed layer
106
a
. This is a problem since the thickness of the copper seed layer
106
is already very thin on the walls
110
. Any further removal of copper from the seed layer
106
can present a situation where an insufficient of copper seed layer
106
remains to enable proper electroplating of copper. If too much copper seed layer
106
is removed, copper interconnect lines and copper filled vias may present defects that reduce reliability and performance of an integrated circuit device. For more information on electroplating, reference can be made to U.S. Pat. No. 5,882,498, which illustrates conventional techniques for electroplating copper materials. This U.S. Patent is hereby incorporated by reference.
In view of the foregoing, there is a need for a method for forming copper interconnect features that do not suffer from the aforementioned problems. In particular, there is a need for a method of copper filling trenches and vias to define copper interconnect features, without compromising the integrity of a copper seed layer used to tart the copper fill process.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a method and apparatus for treating copper seed layers before copper electroplating operations are performed to fill etched trenches and/or vias that define copper interconnect structures. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for making semiconductor interconnect features in a dielectric layer is disclosed. The method includes depositing a copper seed layer over the dielectric layer and into etched features of the dielectric layer having a barrier layer thereon. The copper seed layer is then treated to remove an oxidized layer from over the copper seed layer. The method then moves to electroplating a copper fill layer over the treated copper seed layer. The copper fill layer is configured to fill the etched features of the dielectric layer. In one example, the treating of the copper seed layer includes applying a solution to the copper seed layer including hydrofluoric acid (HF), citric acid, and ammonia mixed in de-ionized water.
In another embodiment, a method for making copper interconnect features in a dielectric layer is disclosed. The method includes depositing a copper seed layer over a barrier layer that is formed over the dielectric layer and into high aspect ratio etched features of the dielectric layer. After the copper seed layer is deposited, the copper seed layer is treated to remove an oxidized layer from over the copper seed layer without removing the copper seed layer. Then, a bulk layer of copper is filled in over the treated copper seed layer. The bulk layer of copper is configured to fill the high aspect ratio etched features of the dielectric layer.
In yet another embodiment, an apparatus for fabricating copper interconnect lines is disclosed. The apparatus includes: (a) a deposition station for depositing a copper seed layer over a barrier layer, the barrier layer lining a dielectric layer and etched features of the dielectric layer of a substrate; (b) a treating module for receiving the substrate and removing a copper oxide layer from over the copper seed layer; and (c) an electroplating module that is connected in-situ with the treating module. The electroplating module is configured to bulk fill copper over the treated copper seed layer and fill the etched features of the dielectric layer.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.
REFERENCES:
patent: 3725224 (1973-04-01), Kendall
patent: 5256565 (1993-10-01), Bernhardt et al.
patent: 5429733 (1995-07-01), Ishida
pat
Lam Research Corporation
Martine & Penilla LLP
Smith-Hicks Erica
Valentine Donald R.
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