Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-08
2001-01-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S632000, C438S661000, C438S672000, C438S678000, C438S680000, C438S681000, C438S685000, C438S687000
Reexamination Certificate
active
06174812
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming ultra large scale integration circuits (ULSI), and, more particularly, to a method for a copper-palladium alloy damascene technology applied to the ULSI circuit fabrication.
2. Description of the Prior Art
Copper has become a promising material to replace aluminum for Ultra Large Scale Integration Circuits (ULSI) interconnection due to its better conductivity and reliability. However, several difficulties are encountered owing to the current process flow of dual damascene and inherent physical properties of copper, as illustrated in
FIG. 1A
to FIG.
1
E. First, after the copper gap-fill electroplating, the high temperature furnace annealing suffers low throughput and potential oxidation hazard since copper is easily and quickly oxidized at low temperature, and, unlike aluminum, forms no self-protective oxide layer to prevent further oxidation. Formation of oxide compounds degrades the electrical and mechanical properties of copper. Second, peeling issues between capped Si
3
N
4
barrier and copper/dielectrics may occur because of bad adhesion. Third, for the present etching process to be used, copper will be exposed during the via etching step in opening low conductivity Si
3
N
4
barrier and potentially cause the device degradation.
An example of a typical copper damascene technology for ULSI circuits fabrication process steps is shown in
FIG. 1A
to FIG.
1
E.
Referring to FIG.
1
A and FIG
1
B, a copper seed
12
is deposited over an oxide layer
10
by means of a barrier TaN
11
, and then a copper gap-fill electroplating layer
13
is electroplated over the oxide layer
10
, which is used as an inter metal dielectric (IMD) layer
10
.
Next, a copper
13
annealing process is carried out in the ambient N
2
. So far as is known, copper
13
is an easily oxidation material so the annealing process must proceed in the ambient N
2
to prevent the oxidation reaction, and then unload the device at the low temperature. The temperature reducing period is in terms of oxidation throughput. The higher oxidation throughput means for the higher taking out temperature. By the way, benefits include reducing the annealing time and cost.
Referring to
FIG. 1C
, a chemical mechanical polishing (CMP) process is carried out by planarizing the copper plating surface
13
.
Referring to
FIG. 1D
, the Si
3
N
4
cap
14
is deposited over the planarized Cu surface
12
to protect it. However, it will face the peeling issues between capped Si
3
N
4
barrier
14
and copper
13
/dielectrics
10
which may occur because of bad adhesion.
Referring to
FIG. 1E
, another inter metal dielectric (IMD) layer
15
is formed over the Si
3
N
4
cap layer
14
of the first IMD layer, and then proceeding the via etching step over the Si
3
N
4
cap layer
14
to connect the first IMD layer
10
and the second IMD layer
15
. For the present etching process to be used, copper will be exposed to the IMD layer
15
during the via etching step in opening the low conductivity Si
3
N
4
barrier
14
and potentially cause the device short or degradation owing to the high diffusivity of copper
13
.
The above problems are hindrances of copper damascene technology for VLSI circuits progress. Now a copper-palladium method is presented to solve those issues as follows.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for alloying copper with palladium, for instance, to resolve the aforementioned difficulties. Doped palladium can expand and expedite the process of high temperature annealing and also serve as an activator for the post chemical mechanical polishing (CMP) barrier capping, allowing the copper diffusion barrier like CoWP being selectively and exclusively deposited on copper interconnect. The advantages of this self-aligned process include reduction of inter metal dielectric (IMD) capacitance and elimination of the peeling problem between barrier and interconnects/dielectrics. In addition, exposure of copper during via etching can be also minimized since CoWP offers low resistivity (~30 &mgr;Ohms-cm) and can thus be preserved for interconnection.
REFERENCES:
patent: 5654232 (1997-08-01), Gardner
patent: 5695810 (1997-12-01), Dubin et al.
patent: 5824599 (1998-10-01), Schacham-Diamond et al.
patent: 5925206 (1999-07-01), Boyko et al.
Hsieh Wen-Yi
Hsiung Chiung-Sheng
Lur Water
Berry Rene{acute over (e)} R.
Harness & Dickey & Pierce P.L.C.
Nelms David
United Microelectronics Corp.
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