Copper damascene manufacturing process

Details Copper damascene manufacturing process Copper damascene manufacturing process

2000-02-04

2001-08-14

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S675000, C438S638000, C438S647000

Reexamination Certificate

active

06274497

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing the multi-level metallic interconnect (MLM) of a semiconductor device. More particularly, the present invention relates to a copper damascene manufacturing process.
2. Description of Related Art
To keep up with the manufacturing cost, deep-submicron devices are now being manufactured. A variety of advanced materials are also employed to increase device operation speed and improve device reliability.
In the backend production of semiconductor devices, current density loading of metal lines is greatly increased due to the large reduction in metal line width. Since aluminum provides little resistance against electromigration, conventional aluminum metal lines are increasingly affected by electromigration problems. Consequently, device reliability will deteriorate if the use of aluminum lines is continued.
To resolve the problems resulting from fabricating deep submicron devices, choosing a metal with a small electromigration such as copper is important. However, copper is a metal that resists the etching action of most conventional gaseous etchants so that copper lines and copper plugs simply cannot be fabricated by a conventional method. Hence, a damascene process must be used instead.
FIGS. 1A through 1F
are schematic cross-sectional views showing the progression of steps in a conventional copper damascene process for producing a copper line and a copper plug.
As shown in
FIG. 1A
, a silicon oxide layer
102
is formed over a substrate
100
. A silicon nitride layer
104
is formed over the silicon oxide layer
102
, and then another silicon oxide layer
106
is formed over the silicon nitride layer
104
. The silicon oxide layer
102
, the silicon nitride layer
104
and the silicon oxide layer
106
can be formed by plasma-enhanced chemical vapor deposition (PECVD), and the layers together serve as an inter-metal dielectric (IMD) layer.
As shown in
FIG. 1B
, photolithographic and etching techniques are used to form a trench line
108
in the silicon oxide layer
106
. The silicon nitride layer
104
serves as an etching stop layer when the trench line
108
is formed so that over-etching is prevented.
As shown in
FIG. 1C
, again using photolithographic and etching techniques, the silicon nitride layer
104
and the silicon oxide layer
102
at the bottom of the trench line
108
are etched to form a via
110
.
As shown in
FIG. 1D
, a metal barrier layer
112
and a copper layer
114
are sequentially formed conformal to the profile of the trench line
108
, the via
110
and the silicon oxide layer
106
. The metal barrier layer
112
and the copper layer
114
can be formed, for example, by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
As shown in
FIG. 1E
, using the copper layer
114
as a seeding layer, copper electroplating is carried out to form a second copper layer
116
over the copper layer
114
.
As shown in
FIG. 1F
, a portion of the metal barrier layer
112
, the copper layers
114
and
116
are removed. Ultimately, only a metal barrier layer
112
a
, copper layers
114
a
and
116
a
are retained inside the trench line
108
and the via
110
. The metal barrier layer
112
, the copper layers
114
and
116
above the silicon oxide layer
106
can be removed by chemical-mechanical polishing (CMP).
As the dimensions of a device shrink, forming a conformal metal barrier layer and a conformal copper seeding layer inside the trench line
108
and the via
110
is becoming harder. This is because of the difficulty in depositing a uniform layer inside an opening having a high aspect ratio (HAR). In addition, forming a copper plug in an opening with a high aspect ratio is likely to result in the formation of a void or a seam in the center of the plug. To form a seeding layer of copper, special copper machines for physical or chemical vapor deposition has to be used. Ultimately, production cost is likely to increase.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a copper damascene process capable of producing a copper plug without the need for special copper machines. In addition, a void and seam free copper plug can be formed inside the via.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a copper damascene process for forming copper plugs. A substrate is provided, and then a conductive structure is formed over the substrate. The conductive structure is a stack that includes an amorphous silicon layer and a metal line, with the amorphous silicon layer sitting on top of the metal line. A dielectric liner layer is formed over the conductive structure and the substrate. A first dielectric layer is formed over the dielectric liner layer, and then a dielectric cap layer is formed over the first dielectric layer. A second dielectric layer is next formed over the dielectric cap layer. The second dielectric layer, the dielectric cap layer, the first dielectric layer and the dielectric liner layer are patterned to form a via. The via exposes a portion of the silicon layer of the conductive structure. Metal barrier spacers are formed on the sidewalls of the via. A copper displacement process is conducted to convert the amorphous silicon layer into a first copper layer. Meanwhile, a portion of the metal barrier spacers is converted into a second copper layer. The second copper layer above the metal barrier spacers is subsequently removed. Using the first copper layer as a seeding layer, a copper electroless plating is carried out to form a copper plug inside the via.
In this invention, a conductive line having an amorphous silicon layer thereon is first formed over a substrate. A multi-level metallic (MLM) layer dielectric is then formed over the conductive line. The MLM dielectric layer is patterned to form a via that exposes a portion of the dielectric silicon layer on the conductive line. Metal barrier spacers are next formed on the sidewalls of the via. A copper displacement process is carried out replacing the dielectric silicon layer on top of the conductive line by a copper layer. Redundant copper on top of the metal barrier spacers is removed. Using the replaced copper layer above the conductive line as a seeding layer, a copper electronless plating is carried out depositing copper anisotropically into the via to form a copper plug.
The copper plug inside the via is formed by an anisotropic growth process starting from the bottom of the via. Thus, even when dimensions of device are reduced to create a high aspect ratio structural opening, no residual void or seam will form in the middle of the copper plug.
In addition, the copper damascene process of this invention can be carried out without using special copper machines for physical or chemical vapor deposition. Production cost thus can be lowered.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6080656 (2000-06-01), Shih et al.
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patent: 6153528 (2000-11-01), Lan
patent: 6156655 (2000-12-01), Huang et al.
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patent: 2000174027 (2000-06-01), None
patent: WO-00/04573 (2000-01-01), None

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