Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-05-22
2001-10-23
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S150000, C438S151000, C438S152000, C438S153000, C438S154000, C438S155000, C438S156000, C438S157000, C438S158000, C438S159000, C438S160000, C438S161000, C438S162000, C438S163000, C438S165000, C438S166000, C438S292000, C438S351000, C438S466000, C438S469000, C438S470000, C438S486000
Reexamination Certificate
active
06306692
ABSTRACT:
CROSS REFERENCE
This application claims the benefit of Korean Patent Application No.
1999-18388
filed on May 21, 1999, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (TFT), and more particularly, to a polysilicon thin film transistor (Poly-Si TFT) and a method of manufacturing the same.
2. Description of Related Art
In order to form a polycrystalline silicon layer as an active layer of the TFT, firstly an intrinsic amorphous silicon layer is first deposited using a plasma chemical vapor deposition (PCVD) technique or a low pressure chemical vapor deposition (LPCVD) technique so that an amorphous silicon layer is formed. Second, the amorphous silicon layer is crystallized through one or a combination of processes that may include a laser annealing technique, a solid phase crystallization (SPC) technique, and a metal induced crystallization (MIC) technique.
FIGS. 1A
to
1
D are cross-sectional views illustrating a known process of manufacturing a coplanar type polysilicon thin film transistor using a metal induced crystallization technique. As shown in
FIG. 1A
, a buffer layer
2
and an amorphous silicon layer
4
are deposited sequentially on a substrate
1
. The buffer layer
2
serves to prevent the extraction of any alkali material from the substrate
1
. A metal layer typically having a thickness of 30ÅA is deposited on the amorphous silicon layer
4
using a sputtering technique. Then, the amorphous silicon layer
4
is crystallized through a long duration heat treatment at a temperature of 500° C. to form a polysilicon layer
10
.
A gate insulating layer
6
and a gate electrode
8
are formed sequentially on the polysilicon layer
10
. The polysilicon layer
10
is patterned in the form of an island that has a width greater than that of both the gate insulating layer
6
and the gate electrode
8
.
Susequently, as shown in
FIG. 1B
, an ion-doping process is carried out to define source and drain regions
12
and
14
using the gate electrode
8
as a mask. At this time, the electrical characteristics of the polysilicon layer
10
depend on a doped impurity gas that is either a p-type impurity gas such as B
2
H
6
or an n-type impurity gas such as PH
3
. The polysilicon layer portion
11
serves as an active area. After the ion-doping process, the activation process follows to activate the gas impurity-doped regions.
Next, as shown in
FIG. 1C
, an interlayer insulator
16
is formed over the whole substrate
1
covering the gate insulating layer
6
and the gate electrode
8
. Interlayer insulator
16
is then etched to form contact holes
26
and
28
, exposing the source and drain regions
12
and
14
, respectively. Then, source and drain electrodes
18
and
20
are formed to contact the source and drain regions
12
and
14
respectively through the contact holes
26
and
28
. In other words, source electrode
18
is formed to contact source region
12
through contact hole
26
, and drain electrode
20
is formed to contact drain region
14
through contact hole
28
. A passivation film
22
is formed over the entire substrate and etched to form a contact hole
30
, exposing a portion of the drain electrode
20
. A transparent conductive electrode is deposited and patterned into a pixel electrode
24
that contacts the exposed portion of the drain electrode
20
through contact hole
30
, thereby completing fabrication of the most important components of the conventional coplanar type Poly-Si TFT.
In the conventional coplanar type Poly-Si TFT described above, however, the active area
11
that is substantially a channel region of the TFT contacts with the metal layer used during the crystallization process, thereby degrading the electrical characteristics of the Poly-Si TFT Besides, since the activation process is an additional production step, the yield can be reduced.
To overcome the above problems, a metal induced lateral crystallization (MILC) technique has been introduced.
FIG. 2
is a cross sectional view illustrating a lateral crystallization method. As shown in
FIG. 2
, the crystallization process of the amorphous silicon layer is not performed as in the FIG.
1
A. Instead, an amorphous silicon layer
10
′ is patterned in the form of an island, and the gate insulating layer
6
and the gate electrode
8
are formed. Then, source and drain regions
12
′ and
14
′ are formed by an ion-doping process. A metal layer
3
is formed over the whole substrate
1
covering the gate electrode
8
. Subsequently, the amorphous silicon layer
10
′ is crystallized by a long duration, high temperature treatment to form a polysilicon layer. At this point, crystal grains of the polysilicon layer grow from both end portions of the intrinsic amorphous silicon area
11
′ to a central portion at the same time that the source and drain regions
12
′ and
14
′ are crystallized. Accordingly, since the active area
11
′ under the gate insulating layer
6
does not contact the metal layer
3
, electrical characteristics of the TFT is improved.
However, lateral crystallization of the intrinsic silicon layer requires a lengthy processing time, thereby causing a low yield. Production time is further lengthened by the additional processing step of activation.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a coplanar type polysilicon thin film transistor having good electrical characteristics and a method of manufacturing the same permitting a short processing time.
In order to achieve the above object, the present invention provides a method of manufacturing a thin film transistor, including: sequentially depositing an amorphous silicon layer, an insulating layer, and a gate metal layer on a substrate; patterning the insulating layer and the gate metal layer to form a gate insulating layer and a gate electrode; treating the amorphous silicon layer with an impurity and a catalyst metal using the gate electrode as a mask; and applying a direct current (DC) voltage to both terminals of the amorphous silicon layer to form a polysilicon layer, the polysilicon layer having source and drain regions and an active area.
The step of treating the amorphous silicon layer with the catalyst metal can be performed after the step of treating the amorphous silicon layer with an impurity. If it is so desired, the step of treating the amorphous silicon layer with the catalyst metal can be performed before the step of treating the amorphous silicon layer with an impurity. Further, the step of treating the amorphous silicon layer with an impurity includes the step of exposing the amorphous silicon layer to a plasma containing a gas selected from a group consisting of PH
3
and B
2
H
6
. Alternatively, the step of treating the amorphous silicon layer with an impurity includes the step of ion-doping using a gas selected from a group consisting of PH
3
and B
2
H
6
. The catalyst metal comprises a material selected from a group consisting of Ni, Pb and Co. The gate insulating layer and the gate electrode are simultaneously patterned. The source and drain regions are spaced apart from the gate insulating layer.
The method of manufacturing a thin film transistor according to the preferred embodiment of the present invention further includes depositing an interlayer insulating layer on the whole substrate covering the gate electrode and the source and drain regions; patterning the interlayer insulating layer to form first and second contact holes; forming the source and drain electrodes contacting the source and drain regions respectively through the first and second contact holes; depositing a passivation film on the whole substrate covering the source and drain electrodes and patterning the passivation film to form a third contact hole; and forming a pixel electrode contacting with the drain electrode through the third contact hole. Further, a method of manufacturing a thin film tr
Kim Sung Ki
Seo Seong Moh
LG. Philips Lcd., Co. LTD
Long Aldridge & Norman LLP
Luu Chuong A
Smith Matthew
LandOfFree
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