Coordinating idle state transitions in multi-core processors

Details Coordinating idle state transitions in multi-core processors Coordinating idle state transitions in multi-core processors

2004-09-03

2008-11-11

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

Reexamination Certificate

active

07451333

ABSTRACT:
Systems and methods of managing processors provide for detecting a command at a core of a processor having a plurality of cores, where the command requests a transition of the core to an idle state. Power consumption of the core is managed based on the command and an idle state status of each of the plurality of cores.

REFERENCES:
patent: 5307003 (1994-04-01), Fairbanks et al.
patent: 5502838 (1996-03-01), Kikinis
patent: 5526487 (1996-06-01), Schiffleger
patent: 5592671 (1997-01-01), Hirayama
patent: 5627412 (1997-05-01), Beard
patent: 5745375 (1998-04-01), Reinhardt et al.
patent: 5787294 (1998-07-01), Evoy
patent: 5812860 (1998-09-01), Horden et al.
patent: 5862368 (1999-01-01), Miller et al.
patent: 5918061 (1999-06-01), Nikjou
patent: 5953685 (1999-09-01), Bogin et al.
patent: 6047248 (2000-04-01), Georgiou et al.
patent: 6363490 (2002-03-01), Senyk
patent: 6415388 (2002-07-01), Browning et al.
patent: 6711691 (2004-03-01), Howard et al.
patent: 6714891 (2004-03-01), Dendinger
patent: 6804790 (2004-10-01), Rhee et al.
patent: 6885233 (2005-04-01), Huard et al.
patent: 6983386 (2006-01-01), Barr
patent: 7043405 (2006-05-01), Orenstien et al.
patent: 7043649 (2006-05-01), Terrell, II
patent: 7134031 (2006-11-01), Flautner
patent: 2002/0083356 (2002-06-01), Dai
patent: 2004/0098631 (2004-05-01), Terrell, II
patent: 0978781 (1999-07-01), None
patent: 1 286 248 (2006-02-01), None
patent: WO-01/35200 (2001-05-01), None
patent: WO-02/17052 (2002-02-01), None
U.S. Appl. No. 10/272,149, filed Oct. 14, 2002: Inventor: Alon Naveh.
U.S. Appl. No. 11/208,935, filed Aug. 22, 2005; Inventor: Julius Mandelblat.
U.S. Appl. No. 11/323,259, filed Dec. 30, 2005; Inventor: Sanjeev Jahagirdar.
U.S. Appl. No. 10/899,674, filed Jul. 27, 2004; Inventor: Alon Naveh.
U.S. Appl. No. 11/323,254, filed Dec. 30, 2005; Inventor: Sanjeev Jahagirdar.
Int'l Application No. PCT/US2005/028699 Int'l Search Report & Written Opinion dated May 8, 2006.
Invitation to Pay Additional Fees and Annex (partial International Search) from PCT/US2005/028699, mailed Mar. 2, 2006, 10 pages.
Non-Final Office Action, Jun. 16, 2005, 13 pgs, Inventor Alon Naveh, Filing Date Oct. 14, 2002.
Non-Final Office Action, Mar. 19, 2007, 18 pgs, Inventor Alon Naveh, Filing Date Jul. 27, 2004.
“42P15271 Notice of Allowance Mailed Jan. 5, 2006 for U.S. Appl. No. 10/272,149”, (Jan. 5, 2006), Whole Document.
“42P19740 OA Mailed Oct. 4, 2007 for U.S. Appl. No. 10/899,674”, (Oct. 4, 2007), Whole Document.

Affiliated with

Also associated with

Rating

Coordinating idle state transitions in multi-core processors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Coordinating idle state transitions in multi-core processors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Coordinating idle state transitions in multi-core processors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4035430