Cooperating memory controllers that share data bus terminals...

Details Cooperating memory controllers that share data bus terminals... Cooperating memory controllers that share data bus terminals...

2009-01-12

2011-12-06

Elmore, Stephen (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S103000, C711S168000

Reexamination Certificate

active

08074033

ABSTRACT:
A memory controller mechanism is operable in a first mode and a second mode. In the first mode, a first memory controller portion of the mechanism can use a first set of data terminals to perform a first external bus access operation (EBAO) and a second memory controller portion of the mechanism can use a second set of data terminals to perform a second EBAO. The first and second EBAO operations may be narrow accesses that occur simultaneously. In the second mode, one of the controllers can use both the first and second sets of data terminals to perform a wider third EBAO. The memory controller mechanism can dynamically switch between first mode and second mode operation. In situations in which one of the sets of data terminals would not otherwise be used, performing wide accesses in the second mode using the one set of data terminals improves bus utilization.

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“AU-SS3000: SDRAM/SRAM/Flash Controller AMBA Subsystem Core”, Aurora VLSI, downloaded from www.auroravlsi.com on Jan. 6, 2009; pp. 1-7.

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