Convolutional interleaver and method for generating memory addre

Details Convolutional interleaver and method for generating memory addre Convolutional interleaver and method for generating memory addre

1997-07-01

2000-03-07

Chan, Eddie P.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data formatting to improve error detection correction...

714701, 714728, 711200, 711202, G06F 1200, G06F 500, G06F 900, G06F 1100

Patent

active

060354275

ABSTRACT:
A convolutional interleaver for interleaving a data stream composed of N number of data with predetermined interleaving level B to randomize the data stream for an error correction, comprising: an input buffer; a memory; an address generating unit; an output buffer; and a controller, and a method for generating an address of the memory are disclosed. In the method for generating an address of the memory, a basic memory of which the number of vertical end is B-1 and horizontal length is (B-1).times.M cell is transformed to an intermediate memory of which the number of vertical end is B-1 and horizontal length is (B/2).times.M cell, and a physical address for accessing the intermediate memory is generated. The physical address is maintained during one clock period, while the memory reads the previous data stored in the memory position corresponding to the physical address during the first half period of the clock and stores the current input data in the same memory position corresponding to the physical address during the latter half period of the clock.

REFERENCES:
patent: 5042033 (1991-08-01), Costa
patent: 5537420 (1996-07-01), Huang

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