Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2003-09-23
2009-10-06
Chaudry, M. Mujtaba K (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C711S127000, C714S786000
Reexamination Certificate
active
07600163
ABSTRACT:
An apparatus for receiving and storing an incoming sequence and for forwarding the bytes of the incoming sequence as an outgoing sequence in a different byte order includes a cache memory and a main memory for storing bytes of the incoming sequence until they can be forwarded as bytes of the outgoing sequence. A control circuit selectively burst mode writes sequences of incoming bytes that need be stored for a relatively long time to blocks of sequential addresses of the main memory, writes individual bytes of the incoming sequence that need be stored for a relatively short time to selected addresses of the cache memory, and reads bytes out of the cache memory and the main memory when needed to form the outgoing sequence.
REFERENCES:
patent: 6035427 (2000-03-01), Kweon
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patent: 6154826 (2000-11-01), Wulf et al.
patent: 6954885 (2005-10-01), Hurt et al.
patent: 6971057 (2005-11-01), Delvaux et al.
patent: 02101937 (2002-12-01), None
Lin Chia-Liang
Wan Bin
Ahmed Enam
Chaudry M. Mujtaba K
Hsu Winston
Realtek Semiconductor Corp.
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