Convolutional encoding using a modified multiplier

Details Convolutional encoding using a modified multiplier Convolutional encoding using a modified multiplier

2006-05-02

2006-05-02

Torres, Joseph (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S786000

Reexamination Certificate

active

07039852

ABSTRACT:
A wireless communications device is disclosed, in which certain digital coding functions are realized according to a modified multiplier architecture. The device includes an encode and modulate function within which convolutional coding function is provided. The convolutional coding function may be realized as a modified parallel multiplier, in which carries among adder units are ignored or not generated. The datastream is applied to the multiplier as the multiplicand, while successive sets of code generator polynomial coefficients are applied as a multiplier. Carry-in and carry-out bits among the adder units are blocked in a coding mode, but passed in a multiplier mode. A similar arrangement of a modified parallel multiplier circuit may be used in generating a scrambling code that is applied prior to transmission.

REFERENCES:
patent: 3678469 (1972-07-01), Freeman et al.
patent: 4598382 (1986-07-01), Sato
patent: 6751773 (2004-06-01), Okabayashi et al.
patent: 2001/0023497 (2001-09-01), Seki
Technical Specification Group Radio Access Network; Multiplexing and Channel Coding (FDD) (Release 1999), “3G TS 25.212 V3.3.0” (Jun. 2000), WWW.3GPP.Org, XP-002202956.

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