Converting bits to vectors in a programmable logic device

Electronic digital logic circuitry – Multifunctional or programmable – Array

Reexamination Certificate

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Details

C326S038000, C326S039000

Reexamination Certificate

active

06844757

ABSTRACT:
A circuit is disclosed for a programmable logic device (PLD) environment that converts unordered bits in a PLD domain to fixed-width vectors in a vector domain. The fixed-width vectors may be used within a vector processing block (VPB) that operates on data in vector format. The PLD includes multiple programmable logic blocks that are configurable by a user. The logic blocks operate on data at a bit level resulting in unordered bits of information in a PLD domain. However, a vector processing block operates on data on a vector level (e.g., 8 bits, 16 bits, 32 bits, 64 bits, etc.). Thus, an interface is coupled between the programmable logic blocks and the vector processing block that converts at least a portion of the unordered bits of information from the PLD domain to one or more fixed-width vectors for use in the vector processing block. The interface may also perform scaling and/or sign extension on the unordered bits, to further free up expensive resources in the PLD domain.

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