Conversion of synchronous/asynchronous signals

Details Conversion of synchronous/asynchronous signals Conversion of synchronous/asynchronous signals

1995-12-04

1997-06-17

Chin, Stephen

Pulse or digital communications

Miscellaneous

375289, 375220, H04L 2538

Patent

active

056404336

ABSTRACT:
A processor controlled test set is disclosed for testing special service circuits of a telecommunication system. A microprocessor controls the overall operation of the test set, while a digital signal processor provides high speed timing signals to the various test circuits for generating the wave forms used in testing, as well as analyzes the test result signals that are converted into digital signals. A calibration of the test generator signals as well as the signal measuring path is carried out prior to the test sequence. The digital signal processor also provides gain control over a talking path to maintain stability thereof. An I/O circuit of the test set provides plural communication paths between remote equipment and the test set to initiate and carry out various tests. Processors in the I/O module are effective to convert the various protocols of the serial data, by way of software, to digital bit streams usable by the test set.

REFERENCES:
patent: 3989892 (1976-11-01), Yoshida et al.
patent: 4078159 (1978-03-01), Lender et al.
patent: 4192974 (1980-03-01), Kiko
patent: 4569062 (1986-02-01), Dallande et al.
"Interface Between Loop Carrier Systems and Loop Testing Systems," Bell Communications Research--Technical Reference TR-TSY-000465, Apr. 1987.
"Digital Data System Channel Interface Specification," Bell System Technical Reference--PUB 62310, Sep. 1983.
VFR5050 Variable Voice Switched Gain Repeater, 1991.

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