Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
2000-09-29
2003-09-02
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S783000
Reexamination Certificate
active
06614122
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of controlling flow of fluid materials and in particular to constructing barriers that restrict flow of an underfill material used to attach a silicon die to a substrate.
2. Discussion of Related Art
In the assembly of high density packaging, such as Organic Land Grid Array (OLGA) laminates that utilize Controlled Collapse Chip Connection (C4) flip-chip die technology, or the direct assembly of a surface mounted flip-chip die to a printed circuit board, an underfill material is typically required. The use of the underfill material, acting as an adhesive, prevents solder bumps on the silicon die from moving as a result of thermal cycling and electrically shorting during the life of the part. In addition, the underfill, acting as a thermal conductor, mediates the thermal miss-match between the silicon die and the organic polymer package (or printed circuit board). Further discussion will deal with C4 flip-chip dies (dies) attached to organic substrates but it is intended that the disclosure will apply to silicon flip-chip dies surface mounted to any number of other types of substrates such as printed circuit board substrates as well.
Referring to
FIGS. 1
a
and
1
b
, the underfill material
102
, a polymer, is applied in a liquid form to flow between the silicon die (die) C4 bumps
104
(shown dashed from opposite side in
FIG. 1
a
) and a die attachment location (die perimeter)
106
on the substrate
108
. The die
103
is assembled to the substrate surface
108
and the excess underfill material
102
, typically an epoxy, may flow out from between the die
103
and substrate
108
surfaces. The underfill
102
may flow sufficiently to cover solder lands
110
on the substrate
108
die side that later will be connected to passive electrical components such as capacitors. To preclude the covering of these solder (covered) lands
110
requires the design of a “keep out” area or zone for die side passive electrical component placement (passive component). Even with the keep out area, if passive electrical components are installed, opens or shorts may be observed due to solder flowing away from the passive electrical components as a result of the underfill material coating the passive electrical components.
REFERENCES:
patent: 4857989 (1989-08-01), Mori et al.
patent: 4926240 (1990-05-01), Regione
patent: 5091770 (1992-02-01), Yamaguchi et al.
Dory Thomas S.
Lee HengGee
Wojewoda Leigh E.
Young David W.
Blakley Sokoloff Taylor & Zafman LLP
Clark Sheila V.
Intel Corporation
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