Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Plural fluid growth steps with intervening diverse operation
Reexamination Certificate
1999-03-09
2001-09-18
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Plural fluid growth steps with intervening diverse operation
Reexamination Certificate
active
06291321
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of creating flat, crack-free low-dislocation-density mismatched semiconductor layers, and of controlling threading dislocation densities in Ge on Si using graded SiGe layers.
The progression of electronic and optoelectronic components and systems is creating a need for more complex system-level functions to be incorporated at the chip level. One of the effects of this demand is to bring ever-increasing pressure to use materials that are not lattice-matched to common substrates.
The technological significance of a totally miscible GeSi system has been well documented. In particular, relaxed graded GeSi buffers have been used as “substrates” for the growth of high electron mobility structures and for the integration of III-V devices on Si. The relaxed graded buffer introduces a 4% lattice mismatch between Si and Ge gradually, resulting in a disperse, three-dimensional misfit dislocation network. Strain-relieving glide of threading dislocations is facilitated, preventing the accumlation of mismatch strain. Because threading dislocations present in the initial layers can also be used to relieve strain in subsequent layers, the nucleation of additional dislocations is suppressed as the graded layer growth progresses. However, a complication arises during thick grades to high Ge concentrations.
The characteristic crosshatch surface roughness and the underlying strain fields of the misfit array can overlap, blocking threading dislocation glide and leading to dislocation pile-ups. The formation of these pile-ups necessitates the nucleation of additional threading dislocations, as the trapped threading dislocations can no longer contribute to strain relief. Growth on offcut Si substrates has been shown to improve surface morphology and decrease the number of pile-ups, but not eliminate them entirely. Therefore, an increase in threading dislocation density and the number of pile-ups is always observed as the thickness of graded layers increases.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a process that allows controlled relaxation of mismatched semiconductor layers so that many different semiconductor materials can be created on common substrates.
It is another object of the invention to provide a method utilizing planarization such as with chemical-mechanical polishing (CMP) which allows for the growth of relaxed graded buffers to 100% Ge without the concomitant increase in threading dislocation density.
It is yet another object of the invention to provide modifications to ultra-high vacuum chemical vapor deposition (UHVCVD) growth procedures which eliminate surface cracks due to the thermal mismatch between Si and Ge and particulate defects due to gas phase nucleation events.
Accordingly, one embodiment of the invention provides a semiconductor structure comprising a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer.
In another embodiment of the invention there is provided a semiconductor structure comprising a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing.
In yet another embodiment of the invention there is provided a semiconductor structure comprising a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer.
In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure comprising providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.
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Currie et al., “Controlling Threading Dislocation in Ge on Si Using Graded SiGe Layers and Chemical-Mechanical Polishing, ” vol. 72 No. 14, p. 1718-1720, Feb. 1998.
Christianson Keith
Massachusetts Institute of Technology
Samuels , Gauthier & Stevens, LLP
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