Controlling the timing of test modes in a multiple processor...

Details Controlling the timing of test modes in a multiple processor... Controlling the timing of test modes in a multiple processor...

2006-08-29

2006-08-29

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C714S030000, C714S034000, C714S035000, C709S227000, C709S229000

Reexamination Certificate

active

07100033

ABSTRACT:
A system includes a first processor, a second processor and a circuit. The first processor includes a first terminal and enters a first test mode in response to the first terminal having a first signal state. The second processor includes a second terminal. The second processor enters a second test mode in response to the second terminal having a second signal state. The circuit may regulate the timing of the first and second signal states to place both the first processor in the first test mode and the second processor in the second test mode at approximately the same time. The circuit may regulate the timing of the signals to cause the first and second processors to resume normal modes of operation at approximately the same time.

REFERENCES:
patent: 6101598 (2000-08-01), Dokic et al.
patent: 6430705 (2002-08-01), Wisor et al.
patent: 6587995 (2003-07-01), Duboc et al.
patent: 6681341 (2004-01-01), Fredenburg et al.
patent: 6718294 (2004-04-01), Bortfeld
patent: 6857084 (2005-02-01), Giles
patent: 6865693 (2005-03-01), McAfee

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