Controlling the slew-rate of an output buffer

Details Controlling the slew-rate of an output buffer Controlling the slew-rate of an output buffer

2009-05-18

2010-12-14

Cho, James (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Pulse shaping

C326S027000

Reexamination Certificate

active

07852110

ABSTRACT:
An output buffer provided according to an aspect of the present invention is designed to generate an output signal with a slew rate that is substantially independent of the threshold voltage of transistors contained within. An output buffer provided according to another aspect of the present invention provides output signals with different slew rates depending on the magnitude of the load capacitance at the output node of the output buffer.

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