Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-03-20
2007-03-20
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000, C710S305000, C710S313000
Reexamination Certificate
active
10464966
ABSTRACT:
A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send out requests for descriptors and receive descriptors in reply to the requests. The descriptors are data structures for describing attributes of the data transfer to and from the devices controlled by the host controller. The host controller further comprises a descriptor cache that is adapted to store prefetched descriptors. The descriptor cache is further adapted to store individual replacement control values for at least a part of the stored prefetched descriptors. The host controller is arranged to replace a stored prefetched descriptor in the descriptor cache by a newly prefetched descriptor based on the replacement control value that is associated with the stored prefetched descriptor. The replacement technique may improve the overall efficiency of the host controller operation.
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Translation of Official Communication, Application No. 102 34 990.8-53, Jul. 29, 2006, pp. 1-3.
Gulick Dale E.
Hesse Siegfried Kay
Advanced Micro Devices , Inc.
Diller Jesse
Kivlin B. Noäl
Peugh Brian R.
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