Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-08
2006-08-08
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C711S100000
Reexamination Certificate
active
07089509
ABSTRACT:
The propagation of a feedback signal, such as a DQS signal generated in response to a read request in a Double Data Rate (DDR) memory system, into a digital host system, such as an ASIC, is controlled by using a programmable delay circuit and detection sequence to compensate for variable I/O delay. The memory system includes a controller and an interface, both on the ASIC, and memory units coupled to the controller through the interface. The interface uses the read request signal, sent by the controller to initiate read operations, to generate a select signal. A programmable delay element inside the interface unit is programmed using a delay value generated by a delay manager unit inside the controller. The programmable delay element delays the select signal, and an enable signal is generated from the delayed select signal, using DQS. The propagation of DQS is controlled by the enable signal. For a number of preferred delay values that are determined through the detection sequence, the enable signal allows DQS to propagate into the ASIC only when DQS is a valid digital signal.
REFERENCES:
patent: 6889334 (2005-05-01), Magro et al.
patent: 2004/0107324 (2004-06-01), Nystuen
patent: 2004/0117742 (2004-06-01), Emberling et al.
Emberling Brian D.
Ramirez Anthony S.
Dinh Paul
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
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