Controlling synchronous serial access to a multiport memory

Details Controlling synchronous serial access to a multiport memory Controlling synchronous serial access to a multiport memory

1995-08-03

1996-06-04

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Sipo/piso

365194, 365221, 36523005, 36523009, G11C 700

Patent

active

055240984

ABSTRACT:
An integrated circuit multiport memory supports synchronous access through a serial port. In operation, a multiport memory of the present invention is coupled to a free running clock signal and a clock enable signal for internally synchronizing serial access. The external clock enable signal prevents incrementing the sequence of serial access when serial access is interrupted. In a synchronous memory of the present invention, the write data signal need not be held after the active edge of the serial clock, since serial data hold time is made independent of serial access memory write timing parameters. When serial data signals are conveyed on a bidirectional line of a asynchronous serial data port of the present invention, a direction control circuit of the present invention is responsive to transfer and write enable signals and independent of the conventional serial output enable signal.

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patent: 5260905 (1993-11-01), Mori

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