Controlling shared memory access ordering in a multi-processing

Details Controlling shared memory access ordering in a multi-processing Controlling shared memory access ordering in a multi-processing

1996-12-17

1999-01-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711147, 711141, G06F 1200

Patent

active

058601260

ABSTRACT:
A technique for controlling memory access ordering in a multi-processing system in which a sequence of accesses to acquire, access and release a shared space of memory is strictly adhered to by use of two specialized instructions for controlling memory access. Two instructions noted as MFDA (Memory Fence Directional--Acquire)and MFDR (Memory Fence Directional--Release) are utilized to control the ordering. The MFDA instruction when encountered in a program operates to ensure that all previous accesses to the specified address (typically to a lock controlling access to the shared space) become visible to other processors before all future accesses are permitted. The MFDR instruction when encountered in a program operates to ensure that all previous accesses become visible to other processors before any future accesses to the specified address. The accesses to the shared space of memory are then located between the MFDA and MFDR instructions and made visible to the other processors in proper order with respect to accesses for acquiring and releasing the shared space.

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