Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-12-27
2002-12-31
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C713S100000
Reexamination Certificate
active
06502156
ABSTRACT:
BACKGROUND
This invention relates generally to processor-based systems and particularly to the control of input/output (I/O) devices coupled to a bus in processor-based systems.
A host bus adapter (HBA) is a device for connecting input/output peripherals to a processor-based system. Host bus adapters may be utilized, for example, for implementing a small computer system interface (SCSI) high speed parallel interface defined by the X3T9.2 Committee of the American National Standards Institute (ANSI). A SCSI interface may connect processor-based systems to SCSI peripheral devices such as hard disk drives, printers, and other devices. A plurality of SCSI devices may be coupled by a SCSI bus. A SCSI bus is a parallel bus that carries data and control signals from the SCSI host bus adapter to the SCSI devices. A SCSI device is a peripheral device that uses the SCSI standard to exchange data and control signals with a processor.
One system of peripheral devices for storing data is called a redundant array of independent disks (RAID). RAID is a data storage method in which data, along with information used for error correction, such as parity bits or Hamming codes, is distributed among two or more hard disk drives in order to improve performance and/or data integrity. A hard disk array may be governed by array management software and a host bus adapter which handles the error correction.
A zero channel RAID (ZCR) adapter is a RAID adapter that uses the system's I/O device to transfer data to the system's storage devices. Generally these adapters are intelligent boards using some form of input/output (I/O) processor. An I/O processor is a processor that handles input/output operations so as to reduce the burden on the host processor. A host processor is a microprocessor which controls the processor-based system and is generally coupled to system memory and chipset.
In one standard motherboard mounted I/O device, interrupts for the I/O device are routed to the system interrupt controller. Implementing hardware-based RAID functionality using such an I/O device is difficult because there is no way of intercepting the I/O data from host memory, performing the RAID function and then forwarding the data to the I/O channel without control of the I/O device's interrupt signals. The system I/O device's Initialization Device Select (IDSEL) signal may also be uncontrolled. When the system boots after a reset, the host basic input/output system (BIOS) initiates a bus scan to find all the bus components installed in the system. The system uses the IDSEL signal to identify an I/O device and then assign the necessary resources. Without independent control of the I/O devices IDSEL and interrupt signals, the host and the ZCR adapter may both attempt to configure the same I/O device. Contention is likely to result during system Power On Self Test (POST) and operating system plug and play operation.
Because processor-based systems use different chipsets and are designed by different design engineers, each platform may control the IDSEL and interrupt signals differently. To accommodate the variations from one platform to another, the host BIOS may also require changes to implement each new functionality. This variation in implementation interferes with developing an industry standard implementation and increases the design burden on platform designers.
Thus there is a need for a platform independent way to allow the control of I/O devices using ZCR adapters.
SUMMARY
In accordance with one aspect, a method includes coupling a host bus adapter on a first bus coupled to a host processor. A host processor configuration cycle is held off using the host bus adapter. An input/output device on the first bus is controlled independently of the host processor.
Other aspects are set forth in the accompanying detailed description and claims.
REFERENCES:
patent: 4509113 (1985-04-01), Heath
patent: 5911055 (1999-06-01), Whiteman et al.
patent: 6070207 (2000-05-01), Bell
patent: 6085333 (2000-07-01), DeKoning et al.
patent: 6148356 (2000-11-01), Archer et al.
Sacker Stephen M.
Warren James D.
Ray Gopal C.
Trop Pruner & Hu P.C.
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