Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Patent
1997-08-18
1999-08-31
Heckler, Thomas M.
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
365218, 711103, G06F 1200
Patent
active
059448377
ABSTRACT:
An operation control method and apparatus are described. The apparatus includes a timer circuit, a blocking circuit and a control circuit. The timer circuit provides a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal. The blocking circuit receives the done signal and provides the done signal as output if the done signal is not blocked when received. The control circuit receives a begin signal indicating that the operation is to be performed and a limit signal to indicate whether or not a condition exists that would prevent the operation from being completed in a single step. If the limit signal indicates the operation can be completed in the single step, the control circuit starts the timing circuit and controls performance of the single step until the done signal is received. If the limit signal indicates the operation cannot be completed in the single step, the control circuit divides the single step into at least two sub-steps, during each sub-step, the control circuit starts the timing circuit and controls performance of the sub-step until the done signal is received. The control circuit blocks output of the done signal from the blocking circuit during each sub-step until a final sub-step. For one embodiment, the operation to be performed is an erase operation specified by a write state machine that specifies an erase block to be erased within a flash memory. Alternately, the operation to be performed is a program operation specified by a write state machine that specifies data to be programmed within a flash memory.
REFERENCES:
patent: 5424992 (1995-06-01), Coffman et al.
patent: 5450360 (1995-09-01), Sato
patent: 5581723 (1996-12-01), Hosbun et al.
Fandrich Mickey Lee
Pathak Bharat
Rozman Rodney R.
Talreja Sanjay S.
Heckler Thomas M.
Intel Corporation
LandOfFree
Controlling flash memory program and erase pulses does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Controlling flash memory program and erase pulses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Controlling flash memory program and erase pulses will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2425442